公开(公告)号：US07345333B2

公开(公告)日：2008-03-18

申请号：US11496605

申请日：2006-07-31

申请人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

发明人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

摘要： A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

摘要翻译： 在形成半导体器件期间使用的方法包括提供晶片衬底组件，其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫，并且衬套设置在开口中。 形成数字线插头的一部分，然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触，然后使用衬垫和底板作为蚀刻停止层，第三次蚀刻电介质层。 形成电容器单元电介质层和电容器顶板，其提供双面容器单元。 形成附加的电介质层，然后蚀刻附加的电介质层，电池顶板和电池电介质以露出数字线插头部分。 最后，形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。

公开(公告)号：US07153746B2

公开(公告)日：2006-12-26

申请号：US11095074

申请日：2005-03-30

申请人： John T. Moore ,  Scott J. DeBoer

发明人： John T. Moore ,  Scott J. DeBoer

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L28/40 ,  H01L21/3144

摘要： A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

公开(公告)号：US06696336B2

公开(公告)日：2004-02-24

申请号：US09855217

申请日：2001-05-14

申请人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

发明人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

摘要： A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

摘要翻译： 在形成半导体器件期间使用的方法包括提供晶片衬底组件，其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫，并且衬套设置在开口中。 形成数字线插头的一部分，然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触，然后使用衬垫和底板作为蚀刻停止层，第三次蚀刻电介质层。 形成电容器电介质层和电容器顶板，其提供双面容器电池。 形成附加的电介质层，然后蚀刻附加的电介质层，电池顶板和电池电介质以露出数字线插头部分。 最后，形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。

公开(公告)号：US06461985B1

公开(公告)日：2002-10-08

申请号：US09393542

申请日：1999-09-10

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

公开(公告)号：US06461982B2

公开(公告)日：2002-10-08

申请号：US08807831

申请日：1997-02-27

申请人： Scott J. DeBoer ,  Randhir P. S. Thakur

发明人： Scott J. DeBoer ,  Randhir P. S. Thakur

IPC分类号： H01L21469

CPC分类号： H01L21/02183 ,  C23C16/40 ,  C23C16/52 ,  H01L21/02274 ,  H01L21/02356 ,  H01L21/316 ,  H01L21/31691 ,  H01L28/40 ,  H01L29/516

摘要： A method of forming a high dielectric oxide film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed. An apparatus for forming the high dielectric oxide film is also described.

摘要翻译： 形成高电介质氧化膜的方法包括在表面上形成高电介质氧化膜。 高电介质氧化物膜具有大于约4的介电常数，并且在膜的形成期间包括存在的多个氧空位。 高电介质氧化膜在其形成期间暴露于足以减少氧空位数的原子氧量。 另外，形成方法中使用的原子氧的量可以作为在形成高电介质氧化膜期间掺入到高电介质氧化膜中的氧的量的函数来控制，或者作为处理室中的原子氧浓度的函数来控制 其中形成高电介质氧化膜。 还描述了用于形成高电介质氧化物膜的装置。

公开(公告)号：US06300671B1

公开(公告)日：2001-10-09

申请号：US09376886

申请日：1999-08-18

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2358

CPC分类号： H01L21/31144 ,  G03F7/091 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/312

摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.

摘要翻译： 一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。 另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。 在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

公开(公告)号：US6093956A

公开(公告)日：2000-07-25

申请号：US100530

申请日：1998-06-18

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/76 ,  H01L23/16

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of the at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

摘要翻译： 一方面，本发明包括一种半导体晶片处理方法，包括在半导体晶片的表面上形成氮化硅层，所述氮化硅层包括至少两个部分，所述至少两个部分中的一个部分产生抵抗 所述至少两个部分中的另一个，并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。 在另一方面，本发明包括减少半导体晶片上的应力的方法，该半导体晶片具有一对相对的表面，并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅，该方法包括提供 所述相对表面中的一个上的氮化硅包括第一部分，第二部分和第三部分，所述第一部分，第二部分和第三部分相对于彼此正向移位，所述第二部分位于第一部分和第三部分之间， 第二部分具有比第一和第三部分更大的化学计算量的硅，与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时，半导体晶片受到的应力较小。 在另一方面，本发明包括半导体晶片组件。

公开(公告)号：US5960294A

公开(公告)日：1999-09-28

申请号：US6126

申请日：1998-01-13

申请人： John K. Zahurak ,  Scott J. DeBoer ,  Randhir P.S. Thakur ,  Mark Fischer

发明人： John K. Zahurak ,  Scott J. DeBoer ,  Randhir P.S. Thakur ,  Mark Fischer

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L28/91

摘要： A method of fabricating capacitors for a dynamic random access memory device reduces double bit failures or shorts in the device. The method includes providing a semiconductor substrate underlying an insulative layer having a plurality of storage cells formed therein electrically connected to the substrate. A first conductive layer of rugged polysilicon, which functions as a first capacitor plate, is formed over the insulative layer in an oxygen-free atmosphere such that the first conductive layer is without natural oxides on the surface thereof. The surface of the first conductive layer in the oxygen-free atmosphere is then conditioned by a rapid thermal nitridization process which forms a silicon nitride film thereon. Thereafter, portions of the first conductive layer are removed from the insulative layer such that the plurality of storage cells are electrically isolated from one another. A dielectric layer is then formed over the first conductive layer and exposed insulative layer, followed by a second conductive layer, functioning as a second capacitor plate, being formed over the dielectric layer to complete the capacitor structure.

摘要翻译： 一种制造用于动态随机存取存储器件的电容器的方法减少了器件中的双位故障或短路。 该方法包括在其上形成有电连接到基板的多个存储单元的绝缘层下方提供半导体基板。 在无氧气氛中的绝缘层上形成用作第一电容器板的凹凸多晶硅的第一导电层，使得第一导电层在其表面上不具有天然氧化物。 然后在无氧气氛中的第一导电层的表面通过在其上形成氮化硅膜的快速热氮化工艺进行调理。 此后，将第一导电层的部分从绝缘层移除，使得多个存储单元彼此电隔离。 然后在第一导电层和暴露的绝缘层上形成电介质层，然后在电介质层上形成用作第二电容器板的第二导电层，以完成电容器结构。

公开(公告)号：US06825522B1

公开(公告)日：2004-11-30

申请号：US09615549

申请日：2000-07-13

申请人： Scott J. DeBoer ,  Don C. Powell

发明人： Scott J. DeBoer ,  Don C. Powell

IPC分类号： H01L24108

CPC分类号： H01L28/60 ,  H01L21/7687 ,  H01L27/10852 ,  H01L28/91

摘要： An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules. The interface layer is then passivated in a nitrogen ambient having a reduced temperature so as to reduce the number of dangling silicon bonds of the lower electrode in a manner that results in reduced thermal damage to neighboring circuit elements.

摘要翻译： 对消耗效应不太敏感的改进的电容器及其提供方法。 电容器包括第一和第二电极以及介于它们之间的绝缘层。 第一电极包括包含n掺杂多晶硅的体层。 第一电极还包括从主体层的第一表面延伸到绝缘层的界面层。 界面层用磷重掺杂，使得第一电极的耗尽区基本上被限制在界面层内。 形成界面层的方法包括在本体层的第一表面上沉积一层六甲基二硅氮烷（HMDS）材料，使得HMDS材料的HMDS分子化学键合到本体层的第一表面。 该方法还包括在磷化氢环境中退火HMDS材料层，以便用PH 3分子代替CH 3甲基。 然后在具有降低的温度的氮气环境中钝化界面层，以便以导致对相邻电路元件的热损伤降低的方式减少下电极的悬挂硅键的数量。

公开(公告)号：US06632719B1

公开(公告)日：2003-10-14

申请号：US09652910

申请日：2000-08-31

申请人： Scott J. DeBoer ,  Whonchee Lee

发明人： Scott J. DeBoer ,  Whonchee Lee

IPC分类号： H01L2120

CPC分类号： H01L28/84 ,  H01L21/32134 ,  H01L28/75

摘要： Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Also disclosed are methods of forming the capacitor structures and capacitors in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.

摘要翻译： 公开了具有沿着电容器结构的上边缘基本上没有半球形晶粒硅的边缘区域的电容器结构和电容器。 所产生的凹陷半球形晶粒硅层在随后的制造过程中减少或防止颗粒与半球形晶粒硅层分离，从而减少缺陷并提高生产量。 还公开了形成电容器结构和电容器的方法，其中用于形成半球形晶粒硅的硅层被选择性地去除以提供基本上不含半球形晶粒硅的边缘区域。