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    Semiconductor device testing system
    1.
    发明授权
    Semiconductor device testing system 失效
    半导体器件测试系统

    公开(公告)号：US06507801B1

    公开(公告)日：2003-01-14

    申请号：US09697026

    申请日：2000-10-25

    申请人： Se-Jang Oh ,  Ki-Sang Kang ,  Jeong-Ho Bang

    发明人： Se-Jang Oh ,  Ki-Sang Kang ,  Jeong-Ho Bang

    IPC分类号： G06F300

    CPC分类号： G01R31/31707 ,  G01R31/3183 ,  G01R31/318371

    摘要： The present invention relates to a semiconductor device testing system having an advanced testing capability for performing tests on a semiconductor device. A system frame includes both normal and high-speed testing formatters, and a test head is arranged in electrical communication with the system frame. Normal PIN drivers are included to operate the testing system at a first frequency to transmit the signals required to perform tests at a normal speed. High-speed PIN drivers are also included to operate the testing system at a second frequency, higher than the first frequency, to transmit the signals required to perform tests at a higher speed. In this manner, the testing system of this invention is able-to achieve superior testing performance while reducing the overall system production cost.

    摘要翻译： 本发明涉及具有用于对半导体器件进行测试的先进测试能力的半导体器件测试系统。 系统框架包括正常和高速测试格式化程序，测试头与系统框架电气通信。 包括正常PIN驱动程序，以第一频率操作测试系统，以正常速度传输执行测试所需的信号。 还包括高速PIN驱动程序，以高于第一个频率的第二个频率操作测试系统，以更高速度传输执行测试所需的信号。 以这种方式，本发明的测试系统能够在降低整个系统生产成本的同时实现优异的测试性能。

    Test apparatus having multiple head boards at one handler and its test method
    2.
    发明授权
    Test apparatus having multiple head boards at one handler and its test method 有权
    在一个处理机上具有多个头板的测试装置及其测试方法

    公开(公告)号：US07602172B2

    公开(公告)日：2009-10-13

    申请号：US12109299

    申请日：2008-04-24

    申请人： Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    发明人： Ae-Yong Chung ,  Sung-Ok Kim ,  Kyeong-Seon Shin ,  Jeong-Ho Bang

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2893 ,  G01R31/01 ,  G01R31/2851

    摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

    摘要翻译： 测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。 由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。 此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。 这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

    Flash memory test system and method capable of test time reduction
    3.
    发明授权
    Flash memory test system and method capable of test time reduction 失效
    闪存测试系统和方法能够测试时间缩短

    公开(公告)号：US07254757B2

    公开(公告)日：2007-08-07

    申请号：US10954834

    申请日：2004-09-29

    申请人： Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    发明人： Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G01R31/28

    CPC分类号： G11C29/56004 ,  G11C29/56 ,  G11C2029/2602

    摘要： A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.

    摘要翻译： 一种能够测试时间缩短的闪存测试系统和使用其的电测试方法。本发明提供一种包括第一存储器和第二存储器的并行测试器。 第一和第二存储器用于将不同的数据提供给多个DUT中的相同地址，从而使得可以在并行测试中进行诸如修整测试，修复测试和无效块掩蔽测试。 因此，进行并行测试来替代以前连续完成的测试。

    Apparatus and method for performing parallel test on integrated circuit devices
    5.
    发明申请
    Apparatus and method for performing parallel test on integrated circuit devices 有权
    在集成电路设备上执行并行测试的装置和方法

    公开(公告)号：US20050007140A1

    公开(公告)日：2005-01-13

    申请号：US10856461

    申请日：2004-05-27

    申请人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    发明人： Woo-Il Kim ,  Hyun-Seop Shim ,  Hyoung-Young Lee ,  Young-Ki Kwak ,  Jeong-Ho Bang ,  Ki-Bong Ju

    IPC分类号： G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  G01R31/26

    CPC分类号： G01R31/31905 ,  G11C2029/2602

    摘要： Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

    摘要翻译： 本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。 测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。 此外，该装置具有至少一个控制单元来控制开关装置。 此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

    Test system of semiconductor device having a handler remote control and method of operating the same
    8.
    发明申请
    Test system of semiconductor device having a handler remote control and method of operating the same 有权
    具有处理器遥控器的半导体器件的测试系统及其操作方法

    公开(公告)号：US20060158211A1

    公开(公告)日：2006-07-20

    申请号：US11252448

    申请日：2005-10-17

    申请人： Ae-Yong Chung ,  Eun-Seok Lee ,  Jeong-Ho Bang ,  Kyeong-Seon Shin ,  Dae-Gab Chi ,  Sung-Ok Kim

    发明人： Ae-Yong Chung ,  Eun-Seok Lee ,  Jeong-Ho Bang ,  Kyeong-Seon Shin ,  Dae-Gab Chi ,  Sung-Ok Kim

    IPC分类号： G01R31/26

    CPC分类号： G01R31/31926 ,  G01R31/31907

    摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

    摘要翻译： 提供了一种用于处理器遥控器的半导体器件的测试系统。 该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据 检查。

    Connector for testing a semiconductor package
    9.
    发明申请
    Connector for testing a semiconductor package 有权
    用于测试半导体封装的连接器

    公开(公告)号：US20060121757A1

    公开(公告)日：2006-06-08

    申请号：US11295208

    申请日：2005-12-05

    申请人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    发明人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

    IPC分类号： H01R4/58

    CPC分类号： G01R1/0483 ,  G01R1/045 ,  G01R1/0466 ,  G01R31/2863

    摘要： In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

    摘要翻译： 在一个实施例中，使用绝缘硅氧烷粉末和导电粉末的混合物制造连接器。 连接器包括由绝缘硅氧烷粉末形成的连接器主体，并且通过将导电粉末迁移到对应于半导体封装的焊料球的连接部位而形成的或更优选地规则排列的导电硅树脂构件。 导电硅树脂构件包括形成为接近连接器主体的上表面并从其突出的高密度导电硅树脂部件，以及在高密度导电硅树脂部件下方大致垂直取向地形成的低密度导电硅树脂部件， 低密度导电硅部件，其具有从连接器本体的下表面露出的下表面。

    Flash memory test system and method capable of test time reduction
    10.
    发明申请
    Flash memory test system and method capable of test time reduction 失效
    闪存测试系统和方法能够测试时间缩短

    公开(公告)号：US20050102589A1

    公开(公告)日：2005-05-12

    申请号：US10954834

    申请日：2004-09-29

    申请人： Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    发明人： Dong-Kyoo Park ,  Jong-Kook Kim ,  Jeong-Ho Bang ,  Sang-Young Choi ,  Eun-Sik Kim

    IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C29/00 ,  G11C29/56

    CPC分类号： G11C29/56004 ,  G11C29/56 ,  G11C2029/2602

    摘要： A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.

    摘要翻译： 一种能够测试时间缩短的闪存测试系统和使用其的电测试方法。本发明提供一种包括第一存储器和第二存储器的并行测试器。 第一和第二存储器用于将不同的数据提供给多个DUT中的相同地址，从而使得可以在并行测试中进行诸如修整测试，修复测试和无效块掩蔽测试。 因此，进行并行测试来替代以前连续完成的测试。