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    Magnetic disk servo wedges with partial track identifiers
    1.
    发明授权
    Magnetic disk servo wedges with partial track identifiers 有权
    带有部分轨迹标识符的磁盘伺服楔

    公开(公告)号：US08922921B1

    公开(公告)日：2014-12-30

    申请号：US14071912

    申请日：2013-11-05

    Applicant: Seagate Technology LLC

    Inventor： Ravi Hebbar ,  Russel Clemmons ,  Bruce D. Buch

    IPC: G11B5/86

    CPC classification number: G11B5/59627 ,  G11B5/59655

    Abstract: A first portion of a track identifier is read from a first servo wedge of a track of a magnetic disk. A second portion of the track identifier is read from a second servo wedge of the track. The second portion includes least-significant bits of the track identifier that are also stored in the first portion. The first and second portions are combined to determine the track identifier for the first and second servo wedges, and the track is identified using the track identifier.

    Abstract translation: 轨道标识符的第一部分从磁盘的轨道的第一伺服楔形件读取。 轨道标识符的第二部分从轨道的第二伺服楔形件读取。 第二部分包括也存储在第一部分中的轨道标识符的最低有效位。 组合第一和第二部分以确定第一和第二伺服楔形的轨道标识符，并且使用轨道标识符识别轨道。

    OPPORTUNISTIC DECODING IN MEMORY SYSTEMS
    2.
    发明申请
    OPPORTUNISTIC DECODING IN MEMORY SYSTEMS 审中-公开
    内存系统中的机会解码

    公开(公告)号：US20140122975A1

    公开(公告)日：2014-05-01

    申请号：US14149460

    申请日：2014-01-07

    Applicant: Seagate Technology LLC

    Inventor： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    IPC: H03M13/11 ,  G06F11/10

    CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/844 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/45 ,  H03M13/451 ,  H03M13/458

    Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

    Abstract translation: 用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。 硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。 软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。 响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。 在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

    Apparatus and method for measuring slider fly height relative to bit patterned media
    3.
    发明授权
    Apparatus and method for measuring slider fly height relative to bit patterned media 有权
    用于测量相对于位图案化介质的滑块飞行高度的装置和方法

    公开(公告)号：US09502063B1

    公开(公告)日：2016-11-22

    申请号：US14987028

    申请日：2016-01-04

    Applicant: Seagate Technology LLC

    Inventor： Wenzhong Zhu ,  Bruce D. Buch ,  Kenneth Haapala

    IPC: G11B5/60 ,  G11B21/21

    CPC classification number: G11B5/6029 ,  G11B5/746 ,  G11B21/21

    Abstract: A slider having a reader and a writer is moved relative to a magnetic bit pattern medium comprising magnetic dots arranged to include a plurality of pre-written servo sectors, data fields defined between servo sectors to which data can be written and erased, and pre-written timing synchronization fields interspersed within the data fields. In some approaches, two different tone patterns are read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two different tone patterns. In other approaches, two odd harmonics are demodulated from a mixed tone pattern read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two odd harmonics.

    Abstract translation: 具有读取器和写入器的滑块相对于包括设置成包括多个预先写入的伺服扇区的磁性点的磁性位图模式介质移动，在可写入和擦除数据的伺服扇区之间定义数据域， 写入的定时同步字段散布在数据字段内。 在一些方法中，从一个或多个定时同步字段读取两种不同的色调图案，并且使用两种不同的色调图案来确定滑块的飞行高度。 在其他方法中，从从一个或多个定时同步场读取的混合色调图案解调两个奇次谐波，并且使用两个奇次谐波确定滑块的飞行高度。

    SECURE EXECUTION ENVIRONMENT CLOCK FREQUENCY HOPPING
    4.
    发明申请
    SECURE EXECUTION ENVIRONMENT CLOCK FREQUENCY HOPPING 审中-公开

    公开(公告)号：US20180309566A1

    公开(公告)日：2018-10-25

    申请号：US15492063

    申请日：2017-04-20

    Applicant: Seagate Technology, LLC

    Inventor： Bruce D. Buch

    IPC: H04L9/00 ,  G06F21/87 ,  G06F1/08 ,  G06F12/02

    CPC classification number: H04L9/003 ,  G06F1/08 ,  G06F12/0246 ,  G06F21/87 ,  G06F2212/7207 ,  G09C1/00 ,  H04L2209/08 ,  H04L2209/12

    Abstract: Apparatus and method for enacting data security in a data storage device, such as by protecting against a differential power analysis (DPA) attack. In some embodiments, a dithered clock signal is generated having a succession of clock pulse segments. Each of the clock pulse segments has a different respective frequency selected in response to a first random number and a different overall duration selected in response to a second random number. The different segment frequencies are selected by supplying the first random number to a lookup table, and the different segment durations are obtained by initializing a timer circuit using the second random number. The dithered clock signal is used to clock a programmable processor during execution of a cryptographic function.

    COMPUTING SYSTEM WITH POWER VARIATION ATTACK COUNTERMEASURES
    5.
    发明申请
    COMPUTING SYSTEM WITH POWER VARIATION ATTACK COUNTERMEASURES 审中-公开

    公开(公告)号：US20180307835A1

    公开(公告)日：2018-10-25

    申请号：US15491654

    申请日：2017-04-19

    Applicant: Seagate Technology, LLC

    Inventor： Bruce D. Buch ,  Nicholas P. Mati ,  Matthew D. Rench

    IPC: G06F21/55 ,  G06F1/08

    CPC classification number: G06F1/08 ,  G06F21/75 ,  G06F21/755 ,  G06F2221/034

    Abstract: A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies. The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.

    Secure execution environment clock frequency hopping
    6.
    发明授权
    Secure execution environment clock frequency hopping 有权

    公开(公告)号：US10200192B2

    公开(公告)日：2019-02-05

    申请号：US15492063

    申请日：2017-04-20

    Applicant: Seagate Technology, LLC

    Inventor： Bruce D. Buch

    IPC: H04L9/00 ,  G06F21/87 ,  G06F1/08 ,  G06F12/02

    Abstract: Apparatus and method for enacting data security in a data storage device, such as by protecting against a differential power analysis (DPA) attack. In some embodiments, a dithered clock signal is generated having a succession of clock pulse segments. Each of the clock pulse segments has a different respective frequency selected in response to a first random number and a different overall duration selected in response to a second random number. The different segment frequencies are selected by supplying the first random number to a lookup table, and the different segment durations are obtained by initializing a timer circuit using the second random number. The dithered clock signal is used to clock a programmable processor during execution of a cryptographic function.

    Opportunistic decoding in memory systems
    7.
    发明授权
    Opportunistic decoding in memory systems 有权
    内存系统中的机会解码

    公开(公告)号：US09122619B2

    公开(公告)日：2015-09-01

    申请号：US14149460

    申请日：2014-01-07

    Applicant: Seagate Technology LLC

    Inventor： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/45 ,  G11C16/26 ,  H03M13/11 ,  H03M13/37

    CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/844 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/45 ,  H03M13/451 ,  H03M13/458

    Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

    Abstract translation: 用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。 硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。 软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。 响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。 在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

    Computing system with power variation attack countermeasures
    8.
    发明授权
    Computing system with power variation attack countermeasures 有权

    公开(公告)号：US10459477B2

    公开(公告)日：2019-10-29

    申请号：US15491654

    申请日：2017-04-19

    Applicant: Seagate Technology, LLC

    Inventor： Bruce D. Buch ,  Nicholas P. Mati ,  Matthew D. Rench

    IPC: G06F21/55 ,  G06F1/08 ,  G06F21/75

    Abstract: A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies.The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.

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