Molecular optoelectronic memory device
    1.
    发明授权
    Molecular optoelectronic memory device 有权
    分子光电存储器件

    公开(公告)号:US07616551B2

    公开(公告)日:2009-11-10

    申请号:US10721574

    申请日:2003-11-25

    IPC分类号: G11B7/00

    摘要: Method for employing optical state-change organic polymer films as information-storage layers in optoelectronic, high-density memories, and high-density optoelectronic memories produced by the method. In certain embodiments, the optical state-change organic polymer films can be manufactured to exhibit two different, stable optical states, one transparent, and one light-absorbing and/or light-reflecting, that can be locally, stably, and reversibly induced by application of an electrical field. In various embodiments, information is digitally encoded in an information-storage layer as bits, the value of each bit represented by the optical state of an area of the information-storage layer corresponding to the bit. In various embodiments, the optical state of a small region of the information-storage layer can be determined by exposing the small region to visible light, and determining whether or not a photodiode layer in an information-storage medium below the information-storage layer generates an electrical current in response to illumination.

    摘要翻译: 在光电子,高密度存储器中使用光学状态变换有机聚合物膜作为信息存储层的方法,以及通过该方法制造的高密度光电存储器。 在某些实施方案中,可以制造光学状态变化的有机聚合物膜以呈现两种不同的,稳定的光学状态,一种透明的,一种光吸收和/或光反射,其可以局部,稳定和可逆地由 应用电场。 在各种实施例中,信息在信息存储层中被数字地编码为比特,每个比特的值由对应于该比特的信息存储层的区域的光学状态表示。 在各种实施例中,信息存储层的小区域的光学状态可以通过将小区域暴露于可见光来确定,并且确定在信息存储层下方的信息存储介质中的光电二极管层是否产生 响应照明的电流。

    Silicon carbide imprint stamp
    2.
    发明授权
    Silicon carbide imprint stamp 失效
    碳化硅印记邮票

    公开(公告)号:US07462292B2

    公开(公告)日:2008-12-09

    申请号:US10766646

    申请日:2004-01-27

    申请人: Heon Lee

    发明人: Heon Lee

    IPC分类号: C03C25/68 B44C1/22

    摘要: A method of fabricating a silicon carbide imprint stamp is disclosed. A mold layer has a cavity formed therein. A spacer is formed in the cavity to reduce a first feature size of the cavity. A casting process is used to form a feature and a foundation layer connected with the feature. The spacer operatively reduces the first feature size of the feature to a second feature size that is less than the lithography limit. The foundation layer and the feature are unitary whole made from a material comprising silicon carbide (SiC), a material that is harder than silicon (Si) alone. Consequently, the silicon carbide imprint stamp has a longer service lifetime because it can endure several imprinting cycles without wearing out or breaking. The longer service lifetime makes the silicon carbide imprint stamp economically feasible to manufacture as the manufacturing cost can be recouped over the service lifetime.

    摘要翻译: 公开了一种制造碳化硅印记印模的方法。 模具层中形成有空腔。 间隔件形成在空腔中以减小空腔的第一特征尺寸。 使用铸造工艺来形成与特征相连的特征和基础层。 间隔件可以将特征的第一特征尺寸减小到小于光刻极限的第二特征尺寸。 基础层和特征是由包括碳化硅(SiC)的材料制成的整体,其是单独比硅(Si)更硬的材料。 因此,碳化硅印记印模具有更长的使用寿命,因为它可以承受几个压印周期而不会磨损或断裂。 更长的使用寿命使得碳化硅印记印模经济上可行,因为制造成本可以在使用寿命内回收。

    Micro-casted silicon carbide nano-imprinting stamp
    3.
    发明授权
    Micro-casted silicon carbide nano-imprinting stamp 失效
    微型碳化硅纳米压印

    公开(公告)号:US07080596B2

    公开(公告)日:2006-07-25

    申请号:US10794928

    申请日:2004-03-05

    IPC分类号: B82B1/00 B29C33/38

    摘要: A micro-casted silicon carbide nano-imprinting stamp and method of making a micro-casted silicon carbide nano-imprinting stamp are disclosed. A micro-casting technique is used to form a foundation layer and a plurality of nano-sized features connected with the foundation layer. The foundation layer and the nano-sized features are unitary whole that is made entirely from a material comprising silicon carbide (SiC) which is harder than silicon (Si) alone. As a result, the micro-casted silicon carbide nano-imprinting stamp has a longer service lifetime because it can endure several imprinting cycles without wearing out or breaking. The longer service lifetime makes the micro-casted silicon carbide nano-imprinting stamp economically feasible to manufacture as the manufacturing cost can be recouped over the service lifetime.

    摘要翻译: 公开了一种微铸造碳化硅纳米压印印模和制造微铸造碳化硅纳米压印印模的方法。 使用微铸造技术形成与基础层连接的基础层和多个纳米尺寸特征。 基础层和纳米尺寸特征是整体整体,其完全由包含比单独的硅(Si)更硬的碳化硅(SiC)的材料制成。 结果,微铸造碳化硅纳米压印印模具有更长的使用寿命,因为它可以承受几个压印周期而不会磨损或断裂。 更长的使用寿命使得微型碳化硅纳米压印印模经济上可行,因为制造成本可以在使用寿命内回收。

    Imprint stamp
    4.
    发明授权

    公开(公告)号:US07060625B2

    公开(公告)日:2006-06-13

    申请号:US10766710

    申请日:2004-01-27

    申请人: Heon Lee

    发明人: Heon Lee

    IPC分类号: H01L21/311

    摘要: A method of fabricating an imprint stamp is disclosed. The imprint stamp includes a plurality of layers of material that are deposited in a deposition order. After deposition, each layer is patterned and then etched to form a portion of an application specific imprint pattern. The portion includes variations in a topography of the layer. The application specific imprint pattern comprises a plurality of features that are defined by the variations in the topographies of all of the layers of material that were deposited, patterned, and etched. The imprint stamp can be used in a soft-lithography process by pressing the application specific imprint pattern into a mask layer in which the application specific imprint pattern is replicated.

    MEGNETIC MEMORY DEVICE
    5.
    发明申请

    公开(公告)号:US20050152182A1

    公开(公告)日:2005-07-14

    申请号:US10753539

    申请日:2004-01-08

    CPC分类号: G11C11/15

    摘要: A random access memory (MRAM) that includes a magnetic memory cell that is switchable between two states under the influence of a magnetic field. The MARAM also includes an electrical bit line coupled to the magnetic memory cell for generating the magnetic field. The electrical bit line includes a conductive component and a magnetic component to guide magnetic flux associated with the magnetic field towards the magnetic memory cell. A thermal insulator is positioned between the conductive portion and the magnetic memory cell, and the magnetic component has at least one guiding portion that extends from the conductive component towards the magnetic memory cell to guide the magnetic flux around at least a portion of the thermal insulator.

    摘要翻译: 一种随机存取存储器(MRAM),其包括在磁场影响下在两个状态之间切换的磁存储单元。 MARAM还包括耦合到磁存储单元的电位线,用于产生磁场。 电位线包括导电部件和磁性部件,以将与磁场相关联的磁通量引向磁存储器单元。 热绝缘体位于导电部分和磁存储单元之间,并且磁性部件具有至少一个引导部分,该引导部分从导电部件朝向磁存储器单元延伸,以引导围绕热绝缘体的至少一部分的磁通量 。

    Method of hardening a nano-imprinting stamp
    6.
    发明授权
    Method of hardening a nano-imprinting stamp 失效
    硬化纳米压印印模的方法

    公开(公告)号:US06916511B2

    公开(公告)日:2005-07-12

    申请号:US10279407

    申请日:2002-10-24

    摘要: A method of forming a hardened nano-imprinting stamp is disclosed. The hardened nano-imprinting stamp includes a plurality of silicon-based nano-sized features that have an hardened shell of silicon carbide, silicon nitride, or silicon carbide nitride. The hardened shell is made harder than the underlying silicon by a plasma carburization and/or a plasma nitridation process. During the plasma process atoms of carbon and/or nitrogen bombard and penetrate a plurality of exposed surfaces of the nano-sized features and chemically react with the silicon to form the hardened shell of silicon carbide, silicon nitride, or silicon carbide nitride.

    摘要翻译: 公开了形成硬化的纳米压印印模的方法。 硬化的纳米压印印模包括多个硅基纳米尺寸特征,其具有碳化硅,氮化硅或碳化硅氮化物的硬化壳。 通过等离子体渗碳和/或等离子体氮化处理使硬化的壳比下面的硅更硬。 在等离子体工艺期间,碳和/或氮原子轰击并穿透纳米尺寸特征的多个暴露表面并与硅发生化学反应以形成碳化硅,氮化硅或碳化硅氮化物的硬化壳。

    Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
    7.
    发明授权
    Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography 有权
    制造用于纳米压印光刻的亚光刻尺寸线和空间图案的方法

    公开(公告)号:US06759180B2

    公开(公告)日:2004-07-06

    申请号:US10133772

    申请日:2002-04-23

    申请人: Heon Lee

    发明人: Heon Lee

    IPC分类号: G03F726

    摘要: A method for fabricating sub-lithographic sized line and space features is disclosed. The method includes the use of conventional microelectronics processing techniques such as photolithographic patterning and etching, polysilicon deposition, polysilicon oxidation, polysilicon oxide etching, polysilicon wet and plasma etching, and chemical mechanical planarization. Polysilicon line features having a feature size that is greater than or equal to a lithography limit are oxidized in a plasma that includes an oxygen gas. The oxidation forms a sub-lithographic sized polysilicon core and an oxidized polysilicon mantel that includes portions along sidewall surfaces of the sub-lithographic sized polysilicon core that also have a sub-lithographic feature size. After planarization and a plasma etch that is selective to either the polysilicon or the oxidized polysilicon, a plurality of sub-lithographic sized line and space patterns are formed. Those line and space patterns can be used for an imprinting stamp for nano-imprint lithography.

    摘要翻译: 公开了一种用于制造次光刻尺寸的线和空间特征的方法。 该方法包括使用常规微电子处理技术,例如光刻图案和蚀刻,多晶硅沉积,多晶硅氧化,多晶氧化物蚀刻,多晶硅湿和等离子体蚀刻以及化学机械平面化。 具有大于或等于光刻极限的特征尺寸的多晶硅线特征在包括氧气的等离子体中被氧化。 氧化形成亚光刻尺寸的多晶硅芯和氧化多晶硅壁,其包括沿着也具有亚光刻特征尺寸的亚光刻尺寸的多晶硅芯的侧壁表面的部分。 在对多晶硅或氧化多晶硅有选择性的平坦化和等离子体蚀刻之后,形成多个亚光刻尺寸的线和空间图案。 这些线和空间图案可用于纳米压印光刻的印记。

    Micro-casted silicon carbide nano-imprinting stamp
    8.
    发明授权
    Micro-casted silicon carbide nano-imprinting stamp 失效
    微型碳化硅纳米压印

    公开(公告)号:US06755984B2

    公开(公告)日:2004-06-29

    申请号:US10279643

    申请日:2002-10-24

    IPC分类号: B44C122

    摘要: A micro-casted silicon carbide nano-imprinting stamp and method of making a micro-casted silicon carbide nano-imprinting stamp are disclosed. A micro-casting technique is used to form a foundation layer and a plurality of nano-sized features connected with the foundation layer. The foundation layer and the nano-sized features are unitary whole that is made entirely from a material comprising silicon carbide (SiC) which is harder than silicon (Si) alone. As a result, the micro-casted silicon carbide nano-imprinting stamp has a longer service lifetime because it can endure several imprinting cycles without wearing out or breaking. The longer service lifetime makes the micro-casted silicon carbide nano-imprinting stamp economically feasible to manufacture as the manufacturing cost can be recouped over the service lifetime.

    摘要翻译: 公开了一种微铸造碳化硅纳米压印印模和制造微铸造碳化硅纳米压印印模的方法。 使用微铸造技术形成与基础层连接的基础层和多个纳米尺寸特征。 基础层和纳米尺寸特征是整体整体,其完全由包含比单独的硅(Si)更硬的碳化硅(SiC)的材料制成。 结果,微铸造碳化硅纳米压印印模具有更长的使用寿命,因为它可以承受几个压印周期而不会磨损或断裂。 更长的使用寿命使得微型碳化硅纳米压印印模经济上可行,因为制造成本可以在使用寿命内回收。

    Low heat loss and small contact area composite electrode for a phase change media memory device
    9.
    发明授权
    Low heat loss and small contact area composite electrode for a phase change media memory device 失效
    用于相变介质存储器件的低热损失和小接触面复合电极

    公开(公告)号:US06746892B2

    公开(公告)日:2004-06-08

    申请号:US10637941

    申请日:2003-08-08

    IPC分类号: H01L4500

    摘要: A low heat loss and small contact area electrode structure for a phase change media memory device is disclosed. The memory device includes a composite electrode that includes a dielectric mandrel that is connected with a substrate and having a tapered shape that terminates at a vertex. An electrically conductive material conformally covers the dielectric mandrel and terminates at a tip. A first dielectric layer covers all of the composite electrode except an exposed portion of the composite electrode that is adjacent to the tip. A phase change media is in contact with the exposed portion. The exposed portion is only a small percentage of an overall surface area of the composite electrode so that a contact footprint between the exposed portion and the phase change media is small relative to a surface area of the phase change media and Joule heat transfer from the phase change media into the composite electrode is reduced.

    摘要翻译: 公开了一种用于相变介质存储器件的低热损失和小的接触面积电极结构。 存储器件包括复合电极,该复合电极包括与基底连接并具有终止于顶点的锥形形状的介质心轴。 导电材料保形地覆盖介电心轴并终止于尖端。 除了与尖端相邻的复合电极的暴露部分之外,第一电介质层覆盖所有复合电极。 相变介质与暴露部分接触。 暴露部分仅是复合电极的整个表面积的一小部分,使得暴露部分和相变介质之间的接触面积相对于相变介质的表面积较小,并且来自相的焦耳热传递 变介质到复合电极减少。

    Phase change material electronic memory structure and method for forming
    10.
    发明授权
    Phase change material electronic memory structure and method for forming 失效
    相变材料电子记忆体结构及其形成方法

    公开(公告)号:US06605821B1

    公开(公告)日:2003-08-12

    申请号:US10142494

    申请日:2002-05-10

    IPC分类号: H01L2902

    摘要: The invention includes an electronic memory structure. The electronic memory structure includes a substrate. A substantially planar first conductor is formed adjacent to the substrate. An interconnection layer is formed adjacent to the first conductor. A phase change material element is formed adjacent to the interconnection layer. The interconnection layer includes a conductive interconnect structure extending from the first conductor to the phase change material element. The interconnect structure includes a first surface physically connected to the first conductor. The interconnect structure further includes a second surface attached to the phase change material element. The second surface area of the second surface is substantially smaller than a first surface area of the first surface. A substantially planar second conductor is formed adjacent to the phase change material element.

    摘要翻译: 本发明包括电子存储器结构。 电子存储器结构包括基板。 基本上平面的第一导体形成为与基板相邻。 互连层与第一导体相邻地形成。 在互连层附近形成相变材料元件。 互连层包括从第一导体延伸到相变材料元件的导电互连结构。 互连结构包括物理地连接到第一导体的第一表面。 互连结构还包括附接到相变材料元件的第二表面。 第二表面的第二表面积基本上小于第一表面的第一表面积。 形成与相变材料元件相邻的基本平坦的第二导体。