公开(公告)号：US20060154460A1

公开(公告)日：2006-07-13

申请号：US11293126

申请日：2005-12-05

申请人： Serah Yun ,  Changki Hong ,  Jaedong Lee ,  Juseon Goo ,  Youngok Kim ,  Jeongheon Park ,  Joonsang Park ,  Keunhee Bai ,  Myoungho Jung

发明人： Serah Yun ,  Changki Hong ,  Jaedong Lee ,  Juseon Goo ,  Youngok Kim ,  Jeongheon Park ,  Joonsang Park ,  Keunhee Bai ,  Myoungho Jung

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897

摘要： In one aspect, a self-aligned contact method is provided in which a substrate having a plurality of structures are spaced apart over a surface of the substrate, and a sacrificial film is deposited over and between the plurality of structures, where a material of the sacrificial film has a given withstand temperature. The sacrificial film is patterned to expose a portion of the substrate adjacent the plurality of structures. An insulating layer is deposited over the sacrificial film and the exposed portion of the substrate, where the depositing of the insulating layer includes a heat treatment at a temperature which is less than the withstand temperature of the sacrificial film material. The insulating layer is planarized to expose the sacrificial film, and the sacrificial film is removed to expose respective areas between the plurality of structures. The respective areas between the plurality of structures are filled with a conductive material.

摘要翻译： 在一个方面，提供一种自对准接触方法，其中具有多个结构的衬底在衬底的表面上间隔开，并且牺牲膜沉积在多个结构之间并且在多个结构之间，其中， 牺牲膜具有给定的耐受温度。 牺牲膜被图案化以暴露与多个结构相邻的衬底的一部分。 绝缘层沉积在牺牲膜和衬底的暴露部分上，其中绝缘层的沉积包括在小于牺牲膜材料的耐受温度的温度下的热处理。 平面化绝缘层以暴露牺牲膜，并且去除牺牲膜以暴露多个结构之间的相应区域。 多个结构之间的各个区域填充有导电材料。

公开(公告)号：US20100200431A1

公开(公告)日：2010-08-12

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01N27/26

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US08228089B2

公开(公告)日：2012-07-24

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01R31/26 ,  G01R31/08 ,  H01L21/66

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US08120089B2

公开(公告)日：2012-02-21

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US20100181610A1

公开(公告)日：2010-07-22

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US09373635B2

公开(公告)日：2016-06-21

申请号：US14801430

申请日：2015-07-16

申请人： Won-Seok Jung ,  Youngok Kim ,  Jihye Kim ,  Kyungjoong Joo

发明人： Won-Seok Jung ,  Youngok Kim ,  Jihye Kim ,  Kyungjoong Joo

IPC分类号： H01L27/115 ,  H01L23/535 ,  H01L29/51 ,  H01L29/423 ,  H01L27/06

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/1157 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.

摘要翻译： 半导体存储器件可以包括沿第一方向布置的堆叠和通过堆叠提供的垂直沟道结构。 每个堆叠可以包括交替层叠在基板上的栅电极和绝缘层。 每个垂直沟道结构可以包括连接到衬底的半导体图案和连接到半导体图案的垂直沟道图案。 每个半导体图案可以具有凹入的侧壁，并且半导体图案可以具有彼此不同的最小宽度。

公开(公告)号：US20100178755A1

公开(公告)日：2010-07-15

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/20

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

公开(公告)号：US20160104719A1

公开(公告)日：2016-04-14

申请号：US14801430

申请日：2015-07-16

申请人： Won-Seok Jung ,  Youngok Kim ,  Jihye Kim ,  Kyungjoong Joo

发明人： Won-Seok Jung ,  Youngok Kim ,  Jihye Kim ,  Kyungjoong Joo

IPC分类号： H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/1157 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.

摘要翻译： 半导体存储器件可以包括沿第一方向布置的堆叠和通过堆叠提供的垂直沟道结构。 每个堆叠可以包括交替层叠在基板上的栅电极和绝缘层。 每个垂直沟道结构可以包括连接到衬底的半导体图案和连接到半导体图案的垂直沟道图案。 每个半导体图案可以具有凹入的侧壁，并且半导体图案可以具有彼此不同的最小宽度。

公开(公告)号：US08076198B2

公开(公告)日：2011-12-13

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。