公开(公告)号：US07457158B2

公开(公告)日：2008-11-25

申请号：US11347216

申请日：2006-02-06

申请人： Seung-Jae Lee ,  Jin-Sung Park

发明人： Seung-Jae Lee ,  Jin-Sung Park

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.

摘要翻译： 提供闪速存储器件，并且闪速存储器件包括存储器单元，连接到所选位线的感测节点，连接到感测节点的负载电路以及连接到感测节点的第一和第二感测和寄存器电路 。 第一感测和寄存器电路被配置为在多位程序操作的初始读取间隔期间根据感测节点的电压电平来存储第一数据值。 负载电路被配置为在多位程序操作的验证读取间隔期间根据存储在第一感测和寄存器电路中的数据值选择性地预充电感测节点。 还提供了一种用于闪速存储器件的多位编程方法。

公开(公告)号：US20070002615A1

公开(公告)日：2007-01-04

申请号：US11347216

申请日：2006-02-06

申请人： Seung-Jae Lee ,  Jin-Sung Park

发明人： Seung-Jae Lee ,  Jin-Sung Park

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.

摘要翻译： 提供闪速存储器件，并且闪速存储器件包括存储器单元，连接到所选位线的感测节点，连接到感测节点的负载电路以及连接到感测节点的第一和第二感测和寄存器电路 。 第一感测和寄存器电路被配置为在多位程序操作的初始读取间隔期间根据感测节点的电压电平来存储第一数据值。 负载电路被配置为在多位程序操作的验证读取间隔期间根据存储在第一感测和寄存器电路中的数据值选择性地预充电感测节点。 还提供了一种用于闪速存储器件的多位编程方法。

公开(公告)号：US07623377B2

公开(公告)日：2009-11-24

申请号：US12255825

申请日：2008-10-22

申请人： Seung-Jae Lee ,  Jin-Sung Park

发明人： Seung-Jae Lee ,  Jin-Sung Park

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.

摘要翻译： 提供闪速存储器件，并且闪速存储器件包括存储器单元，连接到所选位线的感测节点，连接到感测节点的负载电路以及连接到感测节点的第一和第二感测和寄存器电路 。 第一感测和寄存器电路被配置为在多位程序操作的初始读取间隔期间根据感测节点的电压电平来存储第一数据值。 负载电路被配置为在多位程序操作的验证读取间隔期间根据存储在第一感测和寄存器电路中的数据值选择性地预充电感测节点。 还提供了一种用于闪速存储器件的多位编程方法。

公开(公告)号：US08516846B2

公开(公告)日：2013-08-27

申请号：US12062827

申请日：2008-04-04

申请人： Tae-Hee Lee ,  Hong-Hee Park ,  Joon-Hwan Oh ,  Young-Jin Kim ,  Kwang-Ha Suh ,  Jin-Sung Park

发明人： Tae-Hee Lee ,  Hong-Hee Park ,  Joon-Hwan Oh ,  Young-Jin Kim ,  Kwang-Ha Suh ,  Jin-Sung Park

IPC分类号： F25C5/08 ,  F25C1/00 ,  F25C1/04

CPC分类号： F25C1/18 ,  F25C1/08 ,  F25C5/08 ,  F25C2400/10

摘要： An ice maker and a refrigerator having the same include an ice making container which is maintained at a temperature higher than a freezing point of water. Ace core rods having the temperature lower than the freezing point are inserted into the ice making container to cause water in the container to freeze. Accordingly, water at the periphery of the ice making container remains liquid which the water surrounding the ice core rods freezes. As a result, air bubbles generated when the ice is made can be discharged from the liquid portions of the water at the outer edges of the container. This results in ice without trapped air bubbles, which allows excellent transparent ice pieces to be formed. In some embodiments, the exterior surfaces of the ice making container are maintained at a temperature lower than the freezing point of water, and thawing rods maintained at the temperature higher than the freezing point of water are inserted into the center portions of the ice making container. In this embodiment, water at the edges of the ice making container are frozen first, while the water surrounding the thawing rods remains liquid. This also allows air bubbles to escape during formation of the ice, which results in transparent ice pieces.

摘要翻译： 制冰机和具有该制冰机的冰箱包括保持在比水的冰点高的温度的制冰容器。 将具有低于凝固点温度的Ace芯棒插入制冰容器中，使容器内的水冻结。 因此，制冰容器周围的水保持液体，冰芯棒周围的水冻结。 结果，当制冰时产生的气泡可以从容器的外边缘处的水的液体部分排出。 这导致没有被捕获的气泡的冰，这允许形成优异的透明冰块。 在一些实施例中，制冰容器的外表面保持在低于水的凝固点的温度，并且保持在高于水的凝固点的温度的解冻杆被插入制冰容器的中心部分 。 在该实施例中，首先冻结制冰容器边缘处的水，同时围绕解冻杆的水保持液体。 这也允许在形成冰期间气泡逸出，这导致透明的冰块。

公开(公告)号：US08164954B2

公开(公告)日：2012-04-24

申请号：US13224101

申请日：2011-09-01

申请人： Jin-Sung Park

发明人： Jin-Sung Park

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided.

摘要翻译： 一种包括第一和第二存储区域的非易失性存储器件，以及被配置为控制第一和第二存储区域的控制逻辑，其中当在第二存储区域的程序操作通过之前第一存储区域的程序操作被通过时， 控制逻辑完成第一存储区域的编程操作并且继续提供第二存储区域的编程操作。

公开(公告)号：US20100026169A1

公开(公告)日：2010-02-04

申请号：US12382743

申请日：2009-03-23

申请人： Jong-Han Jeong ,  Tae-Kyung Ahn ,  Jae-Kyeong Jeong ,  Jin-Sung Park ,  Hun-Jung Lee ,  Hyun-Soo Shin ,  Yeon-Gon Mo

发明人： Jong-Han Jeong ,  Tae-Kyung Ahn ,  Jae-Kyeong Jeong ,  Jin-Sung Park ,  Hun-Jung Lee ,  Hyun-Soo Shin ,  Yeon-Gon Mo

IPC分类号： H01J1/62 ,  H01L29/10 ,  H01L21/16 ,  H01L29/08

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L29/7869

摘要： Disclosed is a thin film transistor which has an oxide semiconductor as an activation layer, a method of manufacturing the same and a flat panel display device having the same. The thin film transistor includes an oxide semiconductor layer formed on a substrate and including a channel region, a source region and a drain region, a gate electrode insulated from the oxide semiconductor layer by a gate insulating film, and source electrode and drain electrode which are coupled to the source region and the drain region, respectively. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.

摘要翻译： 公开了具有氧化物半导体作为活化层的薄膜晶体管，其制造方法和具有该活性层的平板显示装置。 薄膜晶体管包括形成在基板上的氧化物半导体层，其包括沟道区域，源极区域和漏极区域，通过栅极绝缘膜与氧化物半导体层绝缘的栅极电极以及源极电极和漏极电极 耦合到源区和漏区。 氧化物半导体层包括第一层部分和第二层部分。 第一层部分具有第一厚度和第一载流子浓度，并且第二层部分具有第二厚度和第二载流子浓度。 第二载流子浓度低于第一载流子浓度。

公开(公告)号：US07286411B2

公开(公告)日：2007-10-23

申请号：US11167984

申请日：2005-06-27

申请人： Jin-Sung Park ,  Myong-Jae Kim ,  Seung-Keun Lee

发明人： Jin-Sung Park ,  Myong-Jae Kim ,  Seung-Keun Lee

IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C5/06

CPC分类号： G11C8/08 ,  G11C16/08

摘要： The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage, and a word line driver for driving a word line in responsive to a voltage of the control node. The second voltage is set to a ground voltage during an erase operation. The third voltage is set to a power voltage during the erase operation.

摘要翻译： 本文公开的发明是非易失性存储器件。 非易失性存储器件包括：连接在第一电压和控制节点之间并由第二电压控制的第一晶体管; 连接在第一电压和控制节点之间并由第三电压控制的第二晶体管，以及用于响应于控制节点的电压驱动字线的字线驱动器。 在擦除操作期间将第二电压设置为接地电压。 在擦除操作期间将第三电压设置为电源电压。

公开(公告)号：US20060133145A1

公开(公告)日：2006-06-22

申请号：US11283646

申请日：2005-11-21

申请人： Jin-Sung Park ,  Dae-Seok Byeon

发明人： Jin-Sung Park ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.

公开(公告)号：US20060082411A1

公开(公告)日：2006-04-20

申请号：US11167983

申请日：2005-06-27

申请人： Jin-Sung Park ,  Dae-Seok Byeon

发明人： Jin-Sung Park ,  Dae-Seok Byeon

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： Disclosed is a voltage regulator capable of reducing a set-up time. A driver is connected between a power supply terminal and the output terminal, and supplies a power supply voltage to the output terminal in response to a signal of a control node. A first signal generator provides a first signal to the control node when a voltage of the output terminal is lower than the target voltage. A second signal generator provides a second signal to the control node for a predetermined period of time when the voltage of the output terminal becomes higher than a detection voltage while the first signal generator is providing the first signal to the control node.

摘要翻译： 公开了一种能够减少设置时间的电压调节器。 驱动器连接在电源端子和输出端子之间，并且响应于控制节点的信号将电源电压提供给输出端子。 当输出端子的电压低于目标电压时，第一信号发生器向控制节点提供第一信号。 当第一信号发生器向控制节点提供第一信号时，第二信号发生器在输出端的电压变得高于检测电压的预定时间段内向控制节点提供第二信号。

公开(公告)号：US20060078452A1

公开(公告)日：2006-04-13

申请号：US11034821

申请日：2005-01-14

申请人： Jin-Sung Park ,  Dong-Koo Shin ,  Cheol-Hwan Kim ,  Hyo-Keun Park ,  Yang-Hee Cho ,  In-Hwe Koo ,  Nam-Kyu Cho

发明人： Jin-Sung Park ,  Dong-Koo Shin ,  Cheol-Hwan Kim ,  Hyo-Keun Park ,  Yang-Hee Cho ,  In-Hwe Koo ,  Nam-Kyu Cho

IPC分类号： F04C2/00 ,  F01C1/02 ,  F04C18/00

CPC分类号： F04C23/008 ,  F04C29/026

摘要： An oil discharge reducing device for a scroll compressor comprises: a refrigerant guiding mechanism for guiding a refrigerant gas of high pressure discharged through a discharge opening of the fixed scroll to a rotor of the driving motor; and an oil separating mechanism penetrated through the rotor and for separating oil contained in the refrigerant gas by a centrifugal force caused by the rotation of the rotor while the refrigerant gas guided by the refrigerant guiding mechanism cools the driving motor as it flows though the driving motor. According to this, an amount of oil leaked to outside of the compressor is minimized, and the driving motor constituting the compressor can be effectively cooled.

摘要翻译： 一种用于涡旋压缩机的排油装置，包括：制冷剂引导机构，用于将通过固定涡旋盘的排放口排出的高压制冷剂气体引导到驱动电动机的转子; 以及分离机构，其穿过转子并且通过由转子旋转引起的离心力分离制冷剂气体中所含的油，同时由制冷剂引导机构引导的制冷剂气体在驱动电动机通过驱动电动机时冷却驱动电机 。 因此，泄漏到压缩机外部的油量被最小化，能够有效地冷却构成压缩机的驱动马达。