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    Erase verify mode to evaluate negative Vt's
    1.
    发明授权
    Erase verify mode to evaluate negative Vt's 有权
    擦除验证模式来评估负Vt

    公开(公告)号：US06545912B1

    公开(公告)日：2003-04-08

    申请号：US09727656

    申请日：2000-11-30

    申请人： Joseph G. Pawletko ,  Shane C. Hollmer ,  Pau-Ling Chen

    发明人： Joseph G. Pawletko ,  Shane C. Hollmer ,  Pau-Ling Chen

    IPC分类号： G11C1606

    CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C16/344 ,  G11C29/50

    摘要： A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory transistor and gradually incremented until a logical HIGH bit is read as a logical LOW bit. By iteratively incrementing Vbias, the erase threshold voltage for each memory transistor can be determined. In one process, the erase threshold voltage for each memory transistor in a memory device is determined and then the memory device is put under stress tests to simulate normal operative conditions. After the stress tests, the erase threshold voltage of each memory transistor can be once again determined to ascertain the change in the erase threshold voltage, i.e., the data retention characteristic, of each memory transistor.

    摘要翻译： 提供了一种方法来确定存储晶体管的擦除阈值电压，从而识别不可用的存储晶体管。 电压被施加到所选择的存储晶体管的公共源，并逐渐增加，直到逻辑高位被读为逻辑低位。 通过迭代地增加Vbias，可以确定每个存储晶体管的擦除阈值电压。 在一个过程中，确定存储器件中每个存储晶体管的擦除阈值电压，然后将存储器件置于压力测试中以模拟正常工作状态。 在应力测试之后，可以再次确定每个存储晶体管的擦除阈值电压，以确定每个存储晶体管的擦除阈值电压（即数据保持特性）的变化。

    Memory system having a program and erase voltage modifier
    2.
    发明授权
    Memory system having a program and erase voltage modifier 有权
    具有编程和擦除电压调节器的存储器系统

    公开(公告)号：US06269025B1

    公开(公告)日：2001-07-31

    申请号：US09500699

    申请日：2000-02-09

    申请人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-Ling Chen

    发明人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-Ling Chen

    IPC分类号： G11C1604

    CPC分类号： G11C5/147 ,  G11C16/12 ,  G11C16/16

    摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.

    摘要翻译： 如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。 存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。 电压值存储装置存储电压值。 电压源接收并将电压值转换为电压。 电压源将电压施加到至少一个存储单元。 电压调节电路也耦合以接收存储的电压值。 电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。 如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。

    Two side decoding of a memory array
    3.
    发明授权
    Two side decoding of a memory array 有权
    存储器阵列的双面解码

    公开(公告)号：US06373742B1

    公开(公告)日：2002-04-16

    申请号：US09689036

    申请日：2000-10-12

    申请人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

    发明人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

    IPC分类号： G11C506

    CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C5/063

    摘要： A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

    摘要翻译： 一种用于从存储器阵列的两侧进行解码的解码器。 解码器位于存储器阵列的两侧。 解码器包括从存储器阵列连接到路由线路的驱动器电路。 为了减小解码器的大小，一些路由线从存储器阵列的一侧延伸，并且剩余的路由线从存储器阵列的另一侧延伸。

    Scheme for page erase and erase verify in a non-volatile memory array
    4.
    发明授权
    Scheme for page erase and erase verify in a non-volatile memory array 有权
    在非易失性存储器阵列中进行页擦除和擦除验证的方案

    公开(公告)号：US5995417A

    公开(公告)日：1999-11-30

    申请号：US175646

    申请日：1998-10-20

    申请人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

    发明人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

    IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

    摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

    摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

    Double boosting scheme for NAND to improve program inhibit characteristics
    6.
    发明授权
    Double boosting scheme for NAND to improve program inhibit characteristics 有权
    NAND的双升压方案，提高程序抑制特性

    公开(公告)号：US06504757B1

    公开(公告)日：2003-01-07

    申请号：US09922415

    申请日：2001-08-03

    申请人： Shane C. Hollmer ,  Pau-Ling Chen ,  Quang Binh

    发明人： Shane C. Hollmer ,  Pau-Ling Chen ,  Quang Binh

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A method for boosting potential in the channel of unselected memory cells on a selected bit-line. In this method, a first voltage is applied to all the word-lines of the memory cells in the string. A second voltage is then applied to word-lines adjacent the selected word lines to isolate the selected memory cell. Next, a programming voltage is applied to the selected word-line. In one embodiment, a time delay is applied between applying the second voltage and applying the third voltages to ensure isolation of the selected memory cell before applying the third voltage.

    摘要翻译： 一种用于在所选位线上提升未选择存储单元的通道中的电位的方法。 在该方法中，对串中的存储单元的所有字线施加第一电压。 然后将第二电压施加到与所选字线相邻的字线，以隔离所选择的存储单元。 接下来，将编程电压施加到所选择的字线。 在一个实施例中，在施加第二电压和施加第三电压之间施加时间延迟，以确保在施加第三电压之前所选择的存储器单元的隔离。

    Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device
    8.
    发明授权
    Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device 失效
    使用闪存设备中的参考单元的信号，并行页缓冲区验证或读取字线上的单元格

    公开(公告)号：US5638326A

    公开(公告)日：1997-06-10

    申请号：US630919

    申请日：1996-04-05

    申请人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

    发明人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

    IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C7/00

    CPC分类号： G11C7/14 ,  G11C16/28

    摘要： A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.

    摘要翻译： 包括具有偏置电路的页缓冲器和参考阵列的闪速存储器，其能够使用页缓冲器并行读取和验证存储单元的字线上的值，而与温度，Vcc和工艺变化无关。 偏置电路包括具有连接到参考单元阵列的源的共源共栅晶体管，其提供单个参考信号。 偏置共源共栅将参考信号耦合到偏置发生器中的偏置反相器的输入，而偏置发生器中的偏置负载晶体管将Vcc耦合到偏置反相器输入。 页面缓冲器包括一组锁存器，每个锁存器通过级联耦合到存储器单元。 每个锁存器中的第一个反相器具有与偏置反相器中的晶体管尺寸匹配的晶体管。 锁存器负载晶体管连接在每个锁存器中的第二反相器的上拉和下拉晶体管之间，并且其大小适于匹配偏置负载晶体管。 偏置负载晶体管和锁存负载晶体管的栅极都耦合到偏置反相器的输出，使得每个锁存器的第一反相器具有镜像偏置反相器的输入的输入。

    System for programming memory cells
    9.
    发明授权
    System for programming memory cells 有权
    用于编程存储单元的系统

    公开(公告)号：US06295228B1

    公开(公告)日：2001-09-25

    申请号：US09514933

    申请日：2000-02-28

    申请人： Joseph G. Pawletko ,  Binh Quang Le ,  Pau-Ling Chen ,  James M. Hong

    发明人： Joseph G. Pawletko ,  Binh Quang Le ,  Pau-Ling Chen ,  James M. Hong

    IPC分类号： G11C1606

    CPC分类号： G11C29/028 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C29/50 ,  G11C2029/5004

    摘要： A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.

    摘要翻译： 编程控制电路根据可由测试设备改变的编程信号值对存储器单元进行编程。 编程控制电路包括信号存储装置，信号输出电路和验证电路。 信号存储装置存储编程信号值。 测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。 信号输出电路耦合到信号存储装置以接收编程信号值。 信号输出电路将编程信号值转换为编程信号，并将编程信号输出到存储单元。 验证电路确定存储器单元是否被成功编程。 如果存储单元未成功编程，编程控制电路会增加编程信号值。