摘要:
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
摘要:
The present invention is directed to a process for complex, high density microcircuits in which thick film dielectric pastes are photolithography patterned into high resolution stencils to produce complementary conductor circuitry patterns, the voids of the developed dielectric stencil are filled with thick film conductor paste, and then there is a cofiring of the conductor and the dielectric. With this new process the number of separate firing operations is reduced. The reduction in the number of firings is important in multilevel hybrid structures.