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1.发明授权公开(公告)号：US06686283B1
公开(公告)日：2004-02-03
申请号：US09498083
申请日：2000-02-04
申请人： Shawn T. Walsh , John E. Campbell , Somit Joshi , James B. Friedmann , Michael J. McGranaghan , Janice D. Makos , Arun Sivasothy , Troy A. Yocum , Jaideep Mavoori , Wayne A. Bather , Joe G. Tran , Ju-Ai Ruan , Michelle L. Hartsell , Gregory B. Shinn
发明人： Shawn T. Walsh , John E. Campbell , Somit Joshi , James B. Friedmann , Michael J. McGranaghan , Janice D. Makos , Arun Sivasothy , Troy A. Yocum , Jaideep Mavoori , Wayne A. Bather , Joe G. Tran , Ju-Ai Ruan , Michelle L. Hartsell , Gregory B. Shinn
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31056
摘要： A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
摘要翻译： 一种用于形成用于集成电路的平面隔离结构的方法。 在隔离填充材料上形成蚀刻阻挡层，并且执行回蚀以去除衬底的未蚀刻部分上方的材料。 将暴露的填充材料蚀刻并平坦化以形成平面隔离结构。
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公开(公告)号：US06228741B1
公开(公告)日：2001-05-08
申请号：US09228583
申请日：1999-01-11
申请人： Shawn T. Walsh , John E. Campbell , James B. Friedmann , Thomas M. Parrill , Der'E Jan , Joshua J. Robbins , Byron T. Ahlburn , Sue Ellen Crank
发明人： Shawn T. Walsh , John E. Campbell , James B. Friedmann , Thomas M. Parrill , Der'E Jan , Joshua J. Robbins , Byron T. Ahlburn , Sue Ellen Crank
IPC分类号： H01L2176
CPC分类号： H01L21/02063 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/31051 , H01L21/31116 , H01L21/31612 , H01L21/3185 , H01L21/76224 , H01L21/76232
摘要： A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.
摘要翻译： 给出了在浅沟槽隔离后从活性区域去除过量氧化物的方法，而不使用化学机械抛光。 氮化物掩模在蚀刻隔离沟槽期间保护有源区。 沟槽用氧化物填充，使用高密度等离子体沉积，其同时蚀刻，在隔离沟槽周围提供倾斜的轮廓。 另外的氮化物层用于在沟槽上提供一个帽，该盖密封到下面的氮化物层。 氮化物的盖层接受图案化的蚀刻，以仅在有效区域上移除盖。 这允许选择性蚀刻去除多余的氧化物，其后可以进行选择性蚀刻去除氮化物层。
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公开(公告)号：US07887875B2
公开(公告)日：2011-02-15
申请号：US10262470
申请日：2002-09-30
IPC分类号： B05D5/12 , C23C16/24 , H01L21/4763
CPC分类号： H01L21/0276 , C23C16/345 , C23C16/56 , G03F7/091
摘要： A silicon rich anti-reflective coating (30) is formed on a layer (10) in which narrow linewidth features are to be formed. Prior to the formation of a photoresist layer (50), the anti-reflecting coating (30) is exposed to excited oxygen species to reduce photoresist poisoning.
摘要翻译： 在要形成窄线宽特征的层（10）上形成富硅抗反射涂层（30）。 在形成光致抗蚀剂层（50）之前，将抗反射涂层（30）暴露于激发的氧物质以减少光致抗蚀剂中毒。
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4.发明授权Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis 有权一种基于晶片的半导体器件的驱动电流的提高方法公开(公告)号：US07153711B2
公开(公告)日：2006-12-26
申请号：US10917037
申请日：2004-08-12
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a drive current for semiconductor devices on a wafer-by-wafer basis. The method for manufacturing semiconductor devices, among other elements, includes patterning gate structures on a substrate (220), each of the gate structures having a profile associated therewith, and obtaining information representative of the profiles of the gate structures (240). In accordance with the present invention the information may then be fed forward to alter a manufacturing parameter associated with a drive current of the semiconductor devices (250).
摘要翻译： 本发明提供了一种半导体器件的制造方法，集成电路的制造方法以及用于提高半导体器件的逐个晶片的驱动电流的方法。 除了其他元件之外，半导体器件的制造方法包括在衬底（220）上图案化栅极结构，每个栅极结构具有与其相关联的轮廓，并且获得表示栅极结构（240）的轮廓的信息。 根据本发明，可以向前馈送信息以改变与半导体器件（250）的驱动电流相关联的制造参数。
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5.发明授权公开(公告)号：US06979648B2
公开(公告)日：2005-12-27
申请号：US10460584
申请日：2003-06-11
IPC分类号： G01R31/26 , G03C5/18 , G06F17/50 , H01L21/00 , H01L21/027 , H01L21/28 , H01L21/302 , H01L21/3213 , H01L21/461 , H01L21/4763 , H01L21/66 , H01L21/768 , H01L23/00
CPC分类号： H01L22/20 , H01L21/0276 , H01L21/28123 , H01L21/32139 , H01L21/76838 , H01L22/12 , Y10S430/151
摘要： A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).
摘要翻译： 提出了一种用于通过实时过程反馈确定抗反射涂层（或底部抗反射涂层）过度蚀刻时间调整的方法。 测量图案化光致抗蚀剂的临界尺寸CD <抗体，并且从大量选择具有中值的第一晶片（101）。 找到第一次t *（102）并用于形成所需的结构。 在第二个时间段，使用第一个晶圆上形成的结构的测量临界尺寸（104）。 最后，发现过蚀刻时间t（x）并用于蚀刻批（106）中剩余的晶片。
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公开(公告)号：US06362111B1
公开(公告)日：2002-03-26
申请号：US09382519
申请日：1999-08-25
IPC分类号： H01L21302
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).
摘要翻译： 一种形成线宽低于0.23μm的多晶硅线的工艺。 多晶硅层（20）沉积在半导体本体（10）上。 一层底部抗反射涂层（BARC）（30）沉积在多晶硅层（20）上。 使用常规光刻（例如，深UV光刻）在BARC层（30）上形成抗蚀剂图案（40）。 使用抗蚀剂图案（40）用HBr / O 2的蚀刻化学品蚀刻BARC层（30），直到检测到端点。 然后使用在BARC和抗蚀剂之间具有大约一对一的选择性的相同蚀刻化学品来对BARC层（30）和抗蚀剂图案（40）进行过蚀刻。 过蚀刻是控制抗蚀剂/ BARC图案中线宽降低的定时蚀刻。 图案（50）的最小尺寸减小到低于光刻工具的实际分辨率极限。 最后，使用减小的宽度图案（50）蚀刻多晶硅层（20）。
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7.发明授权公开(公告)号：US07250372B2
公开(公告)日：2007-07-31
申请号：US11177145
申请日：2005-07-07
IPC分类号： H01L21/302
CPC分类号： H01L22/20 , H01L21/0276 , H01L21/28123 , H01L21/32139 , H01L21/76838 , H01L22/12 , Y10S430/151
摘要： A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).
摘要翻译： 提出了一种用于通过实时过程反馈确定抗反射涂层（或底部抗反射涂层）过度蚀刻时间调整的方法。 测量图案化光致抗蚀剂的临界尺寸CD <抗体，并且从大量选择具有中值的第一晶片（101）。 找到第一次t *（102）并用于形成所需的结构。 在第二个时间段，使用第一个晶圆上形成的结构的测量临界尺寸（104）。 最后，发现过蚀刻时间t（x）并用于蚀刻批（106）中剩余的晶片。
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