公开(公告)号：US4637836A

公开(公告)日：1987-01-20

申请号：US778986

申请日：1985-09-23

申请人： Doris W. Flatley ,  Sheng T. Hsu

发明人： Doris W. Flatley ,  Sheng T. Hsu

IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L21/26

CPC分类号： H01L21/823828 ,  H01L21/32155 ,  H01L21/823857 ,  Y10S438/919

摘要： The ion implantation of a silicon structure isolated from a semiconductor substrate by a layer of silicon dioxide with boron ions to render it p type conductive is improved by initially doping the silicon with phosphorus ions. The presence of the phosphorus ions in the silicon prevents the implanted boron ions from rapidly migrating into the silicon dioxide during annealing.

摘要翻译： 通过用磷离子初始掺杂硅，改善了通过具有硼离子的二氧化硅层与半导体衬底隔离以形成p型导电的硅结构的离子注入。 在硅中存在磷离子防止注入的硼离子在退火过程中迅速迁移到二氧化硅中。

公开(公告)号：US4349584A

公开(公告)日：1982-09-14

申请号：US258431

申请日：1981-04-28

申请人： Doris W. Flatley ,  Sheng T. Hsu

发明人： Doris W. Flatley ,  Sheng T. Hsu

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/3105 ,  Y10S438/978

摘要： A process for defining improved tapered openings in glass coatings requires that passivating layers be formed of a doped silicon oxide having a relatively low flow temperature formed on a layer of undoped silicon oxide. After the contact openings are formed, both oxide layers are heated to a temperature below the flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer, the temperature being insufficient to form a significant oxide growth on the exposed portion of the semiconductor body.

摘要翻译： 用于在玻璃涂层中限定改进的锥形开口的方法要求钝化层由形成在未掺杂的氧化硅层上的相对低的流动温度的掺杂氧化硅形成。 在形成接触开口之后，将两个氧化物层加热到低于掺杂层的流动温度的温度一段足以仅使软化并部分回流掺杂层的时间，该温度不足以形成显着的氧化物生长 半导体本体的暴露部分。

公开(公告)号：US4716451A

公开(公告)日：1987-12-29

申请号：US448724

申请日：1982-12-10

申请人： Sheng T. Hsu ,  Doris W. Flatley

发明人： Sheng T. Hsu ,  Doris W. Flatley

IPC分类号： H01L21/8238 ,  H01L21/322 ,  H01L21/74 ,  H01L27/092 ,  H01L29/78 ,  H01L27/04

CPC分类号： H01L27/0928 ,  H01L21/3221 ,  H01L21/74

摘要： A semiconductor device includes a substrate of single crystalline silicon having the active regions of a semiconductor element, such as the source, drain, channel and gates, along one surface of the substrate, and a thin gettering region of a gettering material in the substrate. The gettering region is spaced from both surfaces of the substrate and is adjacent the active regions of the semiconductor element so as to getter contaminants in the substrate from the area of the substrate containing the semiconductor element.

摘要翻译： 半导体器件包括沿衬底的一个表面具有诸如源极，漏极，沟道和栅极的半导体元件的有源区的单晶硅衬底，以及衬底中吸杂材料的薄吸气区。 吸气区域与衬底的两个表面间隔开并且与半导体元件的有源区域相邻，从而从包含半导体元件的衬底的区域吸收衬底中的污染物。

公开(公告)号：US4999691A

公开(公告)日：1991-03-12

申请号：US453090

申请日：1989-12-22

申请人： Sheng T. Hsu ,  Doris W. Flatley

发明人： Sheng T. Hsu ,  Doris W. Flatley

IPC分类号： H01L21/822 ,  H01L27/06

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： A structure and method for making a pair of MOS field effect transistors (MOSFETs), one stacked upon the other in an integrated circuit device is disclosed. In one embodiment of the device, the active layer of the upper MOSFET is epitaxially grown from an exposed surface of the active layer of the lower MOSFET. In another embodiment, the active layer of the upper MOSFET is polysilicon which, optionally, may be recrystallized. In all embodiments, the pair of MOSFETs share a common gate.

摘要翻译： 公开了一种用于在集成电路器件中彼此堆叠的一对MOS场效应晶体管（MOSFET）的结构和方法。 在器件的一个实施例中，上MOSFET的有源层从下MOSFET的有源层的暴露表面外延生长。 在另一个实施例中，上部MOSFET的有源层是可以重结晶的多晶硅。 在所有实施例中，该对MOSFET共享公共栅极。

公开(公告)号：US4927777A

公开(公告)日：1990-05-22

申请号：US418762

申请日：1989-10-06

申请人： Sheng T. Hsu ,  Doris W. Flatley

发明人： Sheng T. Hsu ,  Doris W. Flatley

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L21/823864

摘要： A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.

摘要翻译： 制造具有源极和漏极延伸的MOS晶体管的方法包括在栅极线和衬底表面之间在单晶硅的衬底的表面上形成具有薄的氧化硅层的栅极线。 期望的导电类型的光剂量的离子被嵌入栅极线的每一侧的基板表面直到栅极线的侧壁。 在栅极线的侧壁上形成热生长氧化硅的间隔物，并且期望的导电类型的离子的剂量被嵌入在栅极线的每一侧的衬底表面中以形成源极和漏极区域。 源极和漏极区域延伸到间隔物，并且具有在隔离物下方的栅极线的侧壁延伸的轻掺杂延伸部。

公开(公告)号：US4662064A

公开(公告)日：1987-05-05

申请号：US762521

申请日：1985-08-05

申请人： Sheng T. Hsu ,  Doris W. Flatley ,  Ronald J. Johansson

发明人： Sheng T. Hsu ,  Doris W. Flatley ,  Ronald J. Johansson

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/316

CPC分类号： H01L21/76819 ,  H01L21/31056

摘要： A multi-level metallization is formed by forming a patterned first level metallization layer on the surface of an isolating layer on a substrate of semiconductor material. A thick planarizing layer, preferably of a glass, is applied over the first level metallization layer and the exposed areas of the insulating layer with the planarizing layer bearing depressions in its surface over the exposed areas of the insulating layer. A photoresist layer is formed on the planarizing layer in the depressions in its surface with the portions of the planarizing layer over the first level metallization layer being exposed. The exposed areas of the planarizing layer are isotropically etched until the surface of the planarizing layer is substantially planar with the bottom of the deepest depression in the planarizing layer. Any photoresist material is removed and the planarizing layer is isotropically etched until its surface is substantially planar with the surface of the first level metallization layer. An inter-level insulating layer is applied over the planarized surfaces of the first level metallization layer at the planarizing layer, and a second level metallization layer is applied over the inter-level insulating layer.

摘要翻译： 通过在半导体材料的衬底上的隔离层的表面上形成图案化的一级金属化层来形成多层金属化。 优选玻璃的厚平坦化层被施加在第一层金属化层和绝缘层的暴露区域上，其中平坦化层在绝缘层的暴露区域上的表面上具有凹陷。 在其表面的凹部中的平坦化层上形成光致抗蚀剂层，使第一层金属化层上的平坦化层的部分露出。 平面化层的曝光区域被各向同性地蚀刻，直到平坦化层的表面与平坦化层中最深凹陷的底部基本平坦。 去除任何光致抗蚀剂材料，并且平面化层被各向同性地蚀刻，直到其表面与第一级金属化层的表面基本平坦。 在平坦化层的第一层金属化层的平坦化表面上施加层间绝缘层，并且在层间绝缘层上施加第二层金属化层。

公开(公告)号：US5439848A

公开(公告)日：1995-08-08

申请号：US997730

申请日：1992-12-30

申请人： Sheng T. Hsu ,  Robert G. Pollachek

发明人： Sheng T. Hsu ,  Robert G. Pollachek

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11

CPC分类号： H01L23/53271 ,  H01L21/76805 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002

摘要： A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

摘要翻译： 公开了一种自对准多电平互连结构及其制造方法。 多级互连结构通过以下步骤制造：（1）形成第一多个间隔开的绝缘层[231-233]，其中第一多个包括顶部绝缘层[233]; （2）形成第二多个间隔开的导体[221,222]并将它们指向定位在绝缘层之间; （3）限定延伸穿过顶部绝缘层[233]的第一孔[233h]。 （4）使用第一孔[233h]通过下面的导体和绝缘层限定一连串的自对准随后的孔[222h，232h，22ih，231h]，每个连续的孔与上面的一个连续并自对准 它; 和（5）限定延伸穿过一连串的自对准孔的贯通导体[223]。 在多层SRAM单元中采用自对准多级互连结构。

公开(公告)号：US4797721A

公开(公告)日：1989-01-10

申请号：US37482

申请日：1987-04-13

申请人： Sheng T. Hsu

发明人： Sheng T. Hsu

IPC分类号： H01L29/08 ,  H01L29/786 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/78609

摘要： An N-channel transistor formed in a layer of semiconductor material disposed on a insulating substrate is disclosed. The source region has a depth less than the thickness of the semiconductor layer so that a P-type region can be formed in the semiconductor layer between the source region and the insulating substrate. This P-type region has an impurity concentration sufficient to prevent the depletion region of the source from extending to the interface between the layer of semiconductor material and the substrate. The P-type region substantially prevents back-channel leakage currents from flowing between the source region and the drain region along the portion of the layer of semiconductor material immediately adjacent the insulating substrate when the device has been irradiated.

摘要翻译： 公开了一种形成在设置在绝缘基板上的半导体材料层中的N沟道晶体管。 源极区域的深度小于半导体层的厚度，从而可以在源极区域和绝缘基板之间的半导体层中形成P型区域。 该P型区域具有足以防止源极的耗尽区域延伸到半导体材料层与衬底之间的界面的杂质浓度。 P型区域基本上防止了背光通道泄漏电流沿着紧邻绝缘基板的半导体材料层的部分在源极区域和漏极区域之间流动，当器件被照射时。

公开(公告)号：US4519126A

公开(公告)日：1985-05-28

申请号：US560459

申请日：1983-12-12

申请人： Sheng T. Hsu

发明人： Sheng T. Hsu

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/283

CPC分类号： H01L21/76889 ,  H01L21/823835

摘要： In order to reduce the mechanical stress that occurs at the interface of a layer of a refractory metal silicide and a layer of silicon dioxide, it is proposed that a buffer layer of polycrystalline silicon be interposed between the two layers. To accomplish this and prior to forming contact openings, the buffer layer of polycrystalline silicon is deposited on the layer of silicon dioxide and the structure is then provided with an apertured mask to define the contact openings. The structure is then initially etched through both the buffer layer and the underlying layer of silicon dioxide in order to expose portions of the buried contact regions followed by a second etch of only the buffer layer to only expose portions of the layer of silicon dioxide in order to form a gate member and any required interconnects. The process further includes the formation of a layer of metal silicide on the interconnects, in the contact openings and on the gate member.

摘要翻译： 为了减少在难熔金属硅化物层和二氧化硅层的界面处发生的机械应力，提出在两层之间插入多晶硅缓冲层。 为了在形成接触开口之前和之前形成接触开口，多晶硅的缓冲层沉积在二氧化硅层上，然后该结构设置有多孔掩模以限定接触开口。 然后，首先通过缓冲层和二氧化硅的下层蚀刻该结构，以便暴露部分埋藏的接触区域，然后仅对缓冲层进行第二次蚀刻，以仅依次暴露部分二氧化硅层 以形成门构件和任何所需的互连。 该方法还包括在互连件上，接触开口中和栅极部件上形成金属硅化物层。

公开(公告)号：US4295266A

公开(公告)日：1981-10-20

申请号：US164681

申请日：1980-06-30

申请人： Sheng T. Hsu

发明人： Sheng T. Hsu

IPC分类号： H01L27/092 ,  H01L21/027 ,  H01L21/033 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/26

CPC分类号： H01L21/76208 ,  H01L21/0271 ,  H01L21/033 ,  H01L21/8238 ,  Y10S438/92

摘要： The method presented may be utilized in manufacturing CMOS integrated circuits either in an isoplanar or in a LOCOS process. The method entails the simultaneous formation of the well region with the oxide isolation regions by a drive-in diffusion which is conducted in a dry oxygen ambient. The utilization of the process insures that compounds of silicon, nitrogen and oxygen will not be present in the bulk silicon where they can effect the quality of gate oxides which are subsequently formed.

摘要翻译： 所提出的方法可以用于在等面或LOCOS工艺中制造CMOS集成电路。 该方法需要通过在干氧环境中进行的驱入扩散同时形成具有氧化物隔离区的阱区。 该方法的利用确保硅，氮和氧的化合物不会存在于体硅中，在这些硅中它们可以影响随后形成的栅极氧化物的质量。