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402 条记录 (耗时 0.025 秒)

    Spin transistor magnetic random access memory device
    1.
    发明授权
    Spin transistor magnetic random access memory device 有权
    旋转晶体管磁性随机存取存储器件

    公开(公告)号：US06753562B1

    公开(公告)日：2004-06-22

    申请号：US10401203

    申请日：2003-03-27

    申请人： Sheng Teng Hsu ,  Jinke Tang ,  Keizo Sakiyama

    发明人： Sheng Teng Hsu ,  Jinke Tang ,  Keizo Sakiyama

    IPC分类号： H01L2976

    CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/5607 ,  H01L29/66984

    摘要： A spin transistor employing the ferromagnetic semiconductor/semiconductor heterojunction is disclosed. The ferromagnetic semiconductor layers form heterojunctions directly on the source and drain of a regular field effect transistor. Using room temperature ferromagnetic semiconductor materials such as iron doped titanium oxide, the spin transistor can have improved spin injection efficiency due to the conductance matching of the ferromagnetic semiconductor with the semiconductor source and drain. The spin transistor further comprises writing plates to modify the magnetic polarization of the ferromagnetic layers to provide memory states. The spin transistor can be used as a memory cell in a magnetic random access memory with potentially large memory signal by utilizing the magnetic moment induced resistivity change.

    摘要翻译： 公开了采用铁磁半导体/半导体异质结的自旋晶体管。 铁磁半导体层直接在常规场效应晶体管的源极和漏极上形成异质结。 使用诸如铁掺杂氧化钛的室温铁磁半导体材料，由于铁磁半导体与半导体源极和漏极的电导匹配，自旋晶体管可以具有改善的自旋注入效率。 自旋晶体管还包括写板以修改铁磁层的磁极化以提供存储状态。 通过利用磁矩感应电阻率变化，自旋晶体管可以用作具有潜在的大存储信号的磁性随机存取存储器中的存储单元。

    Silicon/germanium superlattice thermal sensor
    3.
    发明授权
    Silicon/germanium superlattice thermal sensor 失效
    硅/锗超晶格热传感器

    公开(公告)号：US07442599B2

    公开(公告)日：2008-10-28

    申请号：US11522003

    申请日：2006-09-15

    申请人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

    发明人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

    IPC分类号： H01L21/00

    CPC分类号： H01L31/035254 ,  B82Y20/00 ,  H01L27/14649 ,  H01L31/028 ,  H01L31/101 ,  H01L31/1804 ,  Y02P70/521

    摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

    摘要翻译： 硅/锗（SiGe）超晶格热传感器具有相应的制造方法。 该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。 第一基板与第二基板接合，形成接合基板。 在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。

    Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method
    6.
    发明授权
    Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method 失效
    具有放大的源极/漏极接触区域的加强硅化物源极/漏极MOS晶体管和方法

    公开(公告)号：US06352899B1

    公开(公告)日：2002-03-05

    申请号：US09497626

    申请日：2000-02-03

    申请人： Keizo Sakiyama ,  Sheng Teng Hsu

    发明人： Keizo Sakiyama ,  Sheng Teng Hsu

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66575 ,  H01L29/78618 ,  H01L29/78654

    摘要： A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide. The remaining silicide typically forms silicided source regions and silicided drain regions that extend over a portion of the adjacent isolation regions such that the silicided source/drain regions are larger than the underlying source/drain regions to provide a larger contact area.

    摘要翻译： 提供了一种在有源器件中形成硅化源极/漏极的方法，其中电极具有非常薄的结区域。 在该过程中，相邻的有源区域通过隔离区域分开，通常通过LOCOS隔离，沟槽隔离或SOI / SIMOX隔离。 接触材料，优选硅化物，沉积在晶片和底层结构上，包括栅极和互连电极。 然后使用CMP或另一种合适的刨削工艺将硅化物刨平到接近最高结构高度的高度。 然后使用回蚀工艺或其他合适的工艺将硅化物与电极电隔离，以将硅化物降低到低于栅极或互连电极的高度的高度。 然后将晶片图案化并蚀刻以除去不需要的硅化物。 剩余的硅化物通常形成在相邻隔离区域的一部分上延伸的硅化源区域和硅化物漏极区域，使得硅化源极/漏极区域大于下面的源极/漏极区域以提供更大的接触面积。

    Method for forming an iridium oxide (IrOx) nanowire neural sensor array
    7.
    发明授权
    Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
    形成氧化铱（IrOx）纳米线神经传感器阵列的方法

    公开(公告)号：US07905013B2

    公开(公告)日：2011-03-15

    申请号：US11809959

    申请日：2007-06-04

    申请人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

    IPC分类号： H01K3/10

    CPC分类号： A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

    摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

    摘要翻译： 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

    Method of fabricating a low, dark-current germanium-on-silicon pin photo detector
    8.
    发明授权
    Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
    制造低，暗电流硅 - 硅引脚光电探测器的方法

    公开(公告)号：US07811913B2

    公开(公告)日：2010-10-12

    申请号：US11312967

    申请日：2005-12-19

    申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

    发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

    IPC分类号： H01L21/265

    CPC分类号： H01L31/105 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S438/933

    摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

    摘要翻译： 制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

    Dual-pixel full color CMOS imager
    9.
    发明授权
    Dual-pixel full color CMOS imager 有权
    双像素全彩CMOS成像仪

    公开(公告)号：US07759756B2

    公开(公告)日：2010-07-20

    申请号：US12025618

    申请日：2008-02-04

    申请人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

    发明人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

    IPC分类号： H01L31/00 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/14647 ,  H01L27/14689

    摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.

    摘要翻译： 提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。 两个独立像素用于三色检测。 第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。 两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。 底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。 顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。 单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

    Compound semiconductor-on-silicon wafer with a silicon nanowire buffer layer
    10.
    发明授权
    Compound semiconductor-on-silicon wafer with a silicon nanowire buffer layer 有权
    具有硅纳米线缓冲层的复合半导体硅片

    公开(公告)号：US07723729B2

    公开(公告)日：2010-05-25

    申请号：US12036396

    申请日：2008-02-25

    申请人： Tingkai Li ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Sheng Teng Hsu

    IPC分类号： H01L31/0312 ,  H01L29/20 ,  H01L29/06

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/045 ,  H01L29/0673

    摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

    摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。