公开(公告)号：US20060094178A1

公开(公告)日：2006-05-04

申请号：US11174750

申请日：2005-07-05

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/7833

摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

摘要翻译： 一种通过毫秒退火制造MOS晶体管的方法。 提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。 执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。 毫秒退火激活掺杂区中的掺杂剂。 毫秒退火包括快速加热和1至50毫秒内的快速冷却。

公开(公告)号：US07160804B2

公开(公告)日：2007-01-09

申请号：US11174750

申请日：2005-07-05

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/7833

摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

摘要翻译： 一种通过毫秒退火制造MOS晶体管的方法。 提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。 执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。 毫秒退火激活掺杂区中的掺杂剂。 毫秒退火包括快速加热和1至50毫秒内的快速冷却。

公开(公告)号：US20070131998A1

公开(公告)日：2007-06-14

申请号：US11679087

申请日：2007-02-26

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

公开(公告)号：US20070096186A1

公开(公告)日：2007-05-03

申请号：US11366107

申请日：2006-03-01

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

公开(公告)号：US20050064643A1

公开(公告)日：2005-03-24

申请号：US10943699

申请日：2004-09-17

申请人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

发明人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

IPC分类号： H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876

摘要： A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

摘要翻译： 一种用于在垂直DRAM中形成隔离层的方法。 提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。 在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。 去除图案化的掩模层。 每个第二沟槽填充有用作隔离层的绝缘层。 每个第一导电层被蚀刻以形成多个凹槽。 在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。 沟槽顶部绝缘层形成在每个沟槽的底表面中。 每个第一沟槽填充有用作栅极的第二导电层。

公开(公告)号：US20070292659A1

公开(公告)日：2007-12-20

申请号：US11453015

申请日：2006-06-15

申请人： Chia-Yen Li ,  Pin-Sheng Ho ,  Sheng-Tsung Chen ,  Ching-Sheng Yu ,  Hsiao-Chun Chen ,  Chia-Chih Chang ,  Tsung-Chih Huang

发明人： Chia-Yen Li ,  Pin-Sheng Ho ,  Sheng-Tsung Chen ,  Ching-Sheng Yu ,  Hsiao-Chun Chen ,  Chia-Chih Chang ,  Tsung-Chih Huang

IPC分类号： B32B5/16 ,  B32B9/00 ,  B32B19/00

CPC分类号： G06F3/041 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/25 ,  Y10T428/269

摘要： The present invention discloses a high transmittance touch panel, which comprises a substrate and at least one multi-layer anti-reflection coating structure coated on the front side of the substrate. The multi-layer anti-reflection coating structure is a four-layer structure, and the refractive indexes of those layers are high, low, high, and low sequentially from the side neighboring the substrate. The outmost layer is a protective layer having a refractive index within from 1.3 to 1.5 and a thickness of at least 0.1 μm and a hardness reaching 9H of ASTM-D3363. Via the protective layer, not only the transmittance of the touch panel of the present invention can reach over 92% according to ASTM-D1003, but also the abrasion resistance of the touch panel surface can be enhanced.

摘要翻译： 本发明公开了一种高透光率触摸面板，其包括基板和涂覆在基板正面上的至少一层多层防反射涂层结构。 多层抗反射涂层结构是四层结构，并且这些层的折射率从邻近基板的一侧依次高，低，高和低。 最外层是折射率为1.3〜1.5，厚度为0.1μm以上，硬度达到ASTM-D3363的9H的保护层。 通过保护层，不仅根据ASTM-D1003，本发明的触摸面板的透射率可以达到超过92％，而且可以提高触摸面板表面的耐磨性。

公开(公告)号：US06790735B2

公开(公告)日：2004-09-14

申请号：US10449297

申请日：2003-05-29

申请人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

发明人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/11 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.

公开(公告)号：US06958283B2

公开(公告)日：2005-10-25

申请号：US10690859

申请日：2003-10-22

申请人： Chien-Mao Liao ,  Tzu-En Ho ,  Chang-Rong Wu ,  Chih-How Chang ,  Sheng-Wei Yang ,  Sheng-Tsung Chen ,  Chung-Yuan Lee ,  Wen-Sheng Liao ,  Chen-Chou Huang

发明人： Chien-Mao Liao ,  Tzu-En Ho ,  Chang-Rong Wu ,  Chih-How Chang ,  Sheng-Wei Yang ,  Sheng-Tsung Chen ,  Chung-Yuan Lee ,  Wen-Sheng Liao ,  Chen-Chou Huang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229

摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

公开(公告)号：US20080067569A1

公开(公告)日：2008-03-20

申请号：US11751572

申请日：2007-05-21

申请人： Sheng-Tsung Chen ,  Shiah-Jyh Lin ,  Chung-Yuan Lee

发明人： Sheng-Tsung Chen ,  Shiah-Jyh Lin ,  Chung-Yuan Lee

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

摘要： A method for fabricating a vertical transistor. At least one deep trench is formed in a silicon substrate. A conductive structure and a trench top insulator are successively formed in the deep trench, in which the conductive structure comprises a first doping region and the trench top insulator is below the surface of the silicon substrate. An epitaxial silicon layer is formed on the surface of the silicon substrate. Ion implantation is performed in the epitaxial silicon layer to form a second doping region therein. A gate structure is formed on the trench top insulator, protruding from the surface of the epitaxial silicon layer and adjacent to the sidewalls of the epitaxial silicon layer and the deep trench. A capping layer is formed on the epitaxial silicon layer. The invention also discloses a memory device with a vertical transistor and a method for fabricating the same.

摘要翻译： 一种垂直晶体管的制造方法。 在硅衬底中形成至少一个深沟槽。 在深沟槽中连续地形成导电结构和沟槽顶部绝缘体，其中导电结构包括第一掺杂区域，并且沟槽顶部绝缘体位于硅衬底的表面下方。 在硅衬底的表面上形成外延硅层。 在外延硅层中进行离子注入，以在其中形成第二掺杂区。 栅极结构形成在沟槽顶部绝缘体上，从外延硅层的表面突出并且邻近外延硅层和深沟槽的侧壁。 在外延硅层上形成覆盖层。 本发明还公开了一种具有垂直晶体管的存储器件及其制造方法。

公开(公告)号：US07074700B2

公开(公告)日：2006-07-11

申请号：US10943699

申请日：2004-09-17

申请人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

发明人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

IPC分类号： H01L21/22

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876

摘要： A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

摘要翻译： 一种用于在垂直DRAM中形成隔离层的方法。 提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。 在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。 去除图案化的掩模层。 每个第二沟槽填充有用作隔离层的绝缘层。 每个第一导电层被蚀刻以形成多个凹槽。 在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。 沟槽顶部绝缘层形成在每个沟槽的底表面中。 每个第一沟槽填充有用作栅极的第二导电层。