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    VERTICAL TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    VERTICAL TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF 审中-公开
    垂直晶体管器件及其制造方法

    公开(公告)号：US20070131998A1

    公开(公告)日：2007-06-14

    申请号：US11679087

    申请日：2007-02-26

    申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

    发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

    摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

    摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

    Vertical transistor device and fabrication method thereof
    4.
    发明申请
    Vertical transistor device and fabrication method thereof 审中-公开
    垂直晶体管器件及其制造方法

    公开(公告)号：US20070096186A1

    公开(公告)日：2007-05-03

    申请号：US11366107

    申请日：2006-03-01

    申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

    发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

    摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

    摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

    Memory device and fabrication method thereof
    5.
    发明授权
    Memory device and fabrication method thereof 有权
    存储器件及其制造方法

    公开(公告)号：US07449382B2

    公开(公告)日：2008-11-11

    申请号：US11441313

    申请日：2006-05-24

    申请人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

    发明人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/42392

    摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

    摘要翻译： 公开了一种存储器件。 提供基板。 多个支柱设置在基板上。 每个柱具有多个外延层，具有第一侧壁和第二侧壁。 在支柱之间形成沟槽。 公共底电极设置在沟槽的下部并被节点电介质层包围。 第一绝缘层设置在沟槽内的公共底部电极上。 多个栅极结构设置在第一侧壁和沟槽内。 第二绝缘层设置在沟槽内并与栅极结构相邻。 第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

    Trench-type semiconductor device structure
    6.
    发明授权
    Trench-type semiconductor device structure 有权
    沟槽型半导体器件结构

    公开(公告)号：US07985998B2

    公开(公告)日：2011-07-26

    申请号：US12177756

    申请日：2008-07-22

    申请人： Shian-Jyh Lin ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

    发明人： Shian-Jyh Lin ,  Ming-Cheng Chang ,  Neng Tai Shih ,  Hung-Chang Liao

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L28/55

    摘要： A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.

    摘要翻译： 公开了一种沟槽型半导体器件结构。 该结构包括半导体衬底，栅介质层和衬底沟道结构。 半导体衬底包括具有上部和下部的沟槽。 上部包括形成在其中的导电层。 下部包括形成在其中的沟槽电容器。 栅介质层位于半导体衬底和导电层之间。 具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

    Memory device and fabrication method thereof
    7.
    发明申请
    Memory device and fabrication method thereof 有权
    存储器件及其制造方法

    公开(公告)号：US20070166914A1

    公开(公告)日：2007-07-19

    申请号：US11441313

    申请日：2006-05-24

    申请人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

    发明人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/42392

    摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

    摘要翻译： 公开了一种存储器件。 提供基板。 多个支柱设置在基板上。 每个柱具有多个外延层，具有第一侧壁和第二侧壁。 在支柱之间形成沟槽。 公共底电极设置在沟槽的下部并被节点电介质层包围。 第一绝缘层设置在沟槽内的公共底部电极上。 多个栅极结构设置在第一侧壁和沟槽内。 第二绝缘层设置在沟槽内并与栅极结构相邻。 第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

    METHOD OF PATTERNING METAL ALLOY MATERIAL LAYER HAVING HAFNIUM AND MOLYBDENUM
    8.
    发明申请
    METHOD OF PATTERNING METAL ALLOY MATERIAL LAYER HAVING HAFNIUM AND MOLYBDENUM 有权
    具有铪和钼的金属合金材料层的方法

    公开(公告)号：US20110226736A1

    公开(公告)日：2011-09-22

    申请号：US13118604

    申请日：2011-05-31

    申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

    发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

    IPC分类号： C23F1/02 ,  C23F1/26

    CPC分类号： C23F1/26 ,  H01L21/32134

    摘要： A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

    摘要翻译： 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

    Transistor structure and method of making the same
    10.
    发明授权
    Transistor structure and method of making the same 有权
    晶体管结构及制作方法

    公开(公告)号：US07932555B2

    公开(公告)日：2011-04-26

    申请号：US11949788

    申请日：2007-12-04

    申请人： Pei-Ing Lee ,  Shian-Jyh Lin

    发明人： Pei-Ing Lee ,  Shian-Jyh Lin

    IPC分类号： H01L29/66

    CPC分类号： H01L27/1087 ,  H01L27/10841

    摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.

    摘要翻译： 晶体管结构包括栅极沟槽。 栅极沟槽包括瓶形底部。 瓶形底部包括比其顶部更宽的第一导电材料。 顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。