公开(公告)号：US06850437B2

公开(公告)日：2005-02-01

申请号：US10781921

申请日：2004-02-20

申请人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G01R1/06 ,  G01R31/28 ,  G11C16/02 ,  G11C16/06 ,  G11C16/20 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34

CPC分类号： G11C29/846 ,  G11C16/20 ,  G11C2029/1208

摘要： A nonvolatile semiconductor memory device includes a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

摘要翻译： 非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，配置为比较的第一比较器 具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址 故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出 具有第二存储单元阵列的输出。

公开(公告)号：US06711057B2

公开(公告)日：2004-03-23

申请号：US10234704

申请日：2002-09-05

申请人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Tadayuki Taura ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C1606

CPC分类号： G11C29/846 ,  G11C16/20 ,  G11C2029/1208

摘要： A nonvolatile semiconductor memory device comprises a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

摘要翻译： 非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，被配置为比较的第一比较器 具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址 故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出 具有第二存储单元阵列的输出。

公开(公告)号：US06671203B2

公开(公告)日：2003-12-30

申请号：US10233133

申请日：2002-08-30

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

摘要翻译： 非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。 数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。 用于读取的读出放大器连接到数据线进行读取。 用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

公开(公告)号：US06577538B2

公开(公告)日：2003-06-10

申请号：US10197847

申请日：2002-07-19

申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

公开(公告)号：US06643183B2

公开(公告)日：2003-11-04

申请号：US10196957

申请日：2002-07-19

申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

公开(公告)号：US06795352B2

公开(公告)日：2004-09-21

申请号：US10703005

申请日：2003-11-05

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.

摘要翻译： 半导体存储器包括参考电流发生器，第一和第二电流转换器，用于读出的读出放大器和用于验证的读出放大器。 参考电流发生器根据流过参考单元的电流产生第一电压。 输入第一电压的第一电流转换器各自产生第二电压。 第一电压输入的第二电流转换器各自产生第三电压。 读出放大器，用于选择存储器单元的读取输出数据，将用于读取的数据线的电压与第二电压进行比较。 用于验证输出的读出放大器验证选择存储单元的数据，比较用于验证的数据线的电压和第三电压。

公开(公告)号：US06445618B1

公开(公告)日：2002-09-03

申请号：US10081532

申请日：2002-02-25

申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C800

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

摘要翻译： 在通道擦除EEPROM中，在提供衬底电压的节点N1和字线上提供电压的节点N2之间存在寄生电容。 在擦除存储单元中的数据时，将负电压施加到字线。 开关电路SW1连接在节点N1和节点N2之间。 在节点N1和地之间，连接有开关SW4。 开关SW5连接在节点N2和地之间。 当擦除操作完成时，开关电路SW1首先导通，短路节点N1和节点N2。 此后，开关电路SW4，SW5分别接通，接地节点N1和节点N2。

公开(公告)号：US06373749B1

公开(公告)日：2002-04-16

申请号：US09536391

申请日：2000-03-28

申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C800

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

公开(公告)号：US06222774B1

公开(公告)日：2001-04-24

申请号：US09391180

申请日：1999-09-08

申请人： Toru Tanzawa ,  Akira Umezawa ,  Tadayuki Taura ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Akira Umezawa ,  Tadayuki Taura ,  Shigeru Atsumi

IPC分类号： G11C1606

CPC分类号： G11C16/30 ,  G11C16/08 ,  G11C16/14

摘要： The non-volatile semiconductor memory device comprises memory cell array having a plurality of memory cells, word lines connected to control gates of the memory cells, bit lines connected to drains of the memory cells, a source line connected in common to sources of the memory cells and connected to a well region where the memory cells are formed, a row decoder consisting of a row main decoder and a row sub-decoder for selecting a word line in the memory cell array, a column gate circuits for selecting a bit line in the memory cell array, a control gate driver for biasing a word line in the memory cell array, and an well driver for biasing semiconductor region in which the memory cell array is formed.

摘要翻译： 非易失性半导体存储器件包括具有多个存储器单元的存储单元阵列，连接到存储器单元的控制栅极的字线，连接到存储器单元的漏极的位线，与存储器的源极共同连接的源极线 并连接到形成有存储单元的阱区，由行主解码器和用于选择存储单元阵列中的字线的行子解码器组成的行解码器，用于选择存储单元阵列中的位线的列门电路 存储单元阵列，用于偏置存储单元阵列中的字线的控制栅极驱动器，以及用于偏置形成存储单元阵列的半导体区域的阱驱动器。

公开(公告)号：US06535427B1

公开(公告)日：2003-03-18

申请号：US09707983

申请日：2000-11-08

申请人： Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

发明人： Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

IPC分类号： G11C1626

CPC分类号： G11C7/12 ,  G11C7/20 ,  G11C16/24 ,  G11C16/26

摘要： A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.

摘要翻译： 存储单元连接到基于单元的位线。 基于单元的位线通过Y解码器连接到位线。 位线通过分离电路连接到感测位线。 该感测位线通过偏置电路连接到感测线。 放大器电路将感测线上的信号电压与用于感测数据的参考电压一起放大。 感测线与感测线初始化电路连接，用于将感测线设置为指定电压。 位线与位线初始化电路连接，用于将位线设置为指定电压。 感测线初始化电路和位线初始化电路在放大器电路操作以感测数据之前的给定时间段内被激活。 因此，感测线和位线被设定为规定的电压。