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公开(公告)号：US08910018B2
公开(公告)日：2014-12-09
申请号：US13551485
申请日：2012-07-17
申请人： Shih-Chang Huang , Han-Sung Chen
发明人： Shih-Chang Huang , Han-Sung Chen
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , H03M13/05
摘要： A dynamic error correcting table can be embedded on an integrated circuit memory device. The error correcting table includes entries which are created for data when an error is detected and corrected during a read of the data. During subsequent reads, without intervening write or refresh operations, the entry in the table can be used to correct the error by merging the corrected bit with the data output from the array before it is applied to the ECC logic.
摘要翻译： 动态纠错表可嵌入集成电路存储器件中。 错误校正表包括当在读取数据期间检测到错误并被校正时为数据创建的条目。 在后续读取期间，无需插入写入或刷新操作，表中的条目可用于通过将已更正的位与应用于ECC逻辑之前从阵列输出的数据合并来纠正错误。
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公开(公告)号：US20140026011A1
公开(公告)日：2014-01-23
申请号：US13551485
申请日：2012-07-17
申请人： Shih-Chang Huang , Han-Sung Chen
发明人： Shih-Chang Huang , Han-Sung Chen
CPC分类号： G06F11/1048 , H03M13/05
摘要： A dynamic error correcting table can be embedded on an integrated circuit memory device. The error correcting table includes entries which are created for data when an error is detected and corrected during a read of the data. During subsequent reads, without intervening write or refresh operations, the entry in the table can be used to correct the error by merging the corrected bit with the data output from the array before it is applied to the ECC logic.
摘要翻译： 动态纠错表可嵌入集成电路存储器件中。 错误校正表包括当在读取数据期间检测到错误并被校正时为数据创建的条目。 在后续读取期间，无需插入写入或刷新操作，表中的条目可用于通过将已更正的位与应用于ECC逻辑之前从阵列输出的数据合并来纠正错误。
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公开(公告)号：US09570133B2
公开(公告)日：2017-02-14
申请号：US13713883
申请日：2012-12-13
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.
摘要翻译： 公开了具有字线驱动器和控制电路的存储器电路。 字线驱动器接收第一电压参考信号，第二电压参考信号和输入信号。 字线驱动器具有耦合到字线的输出。 控制电路被配置为通过将输入信号施加到字线驱动器的输入来取消选择字线。 例如，在程序操作中，字线被取消选择以指示字线未被编程，并且另一个字线被选择来被编程。 在取消选择字线并选择另一个字线的操作期间，字线通过字线驱动器的第一p型晶体管和第一n型晶体管两者放电。
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4.发明授权Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits 有权用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置公开(公告)号：US08913445B2
公开(公告)日：2014-12-16
申请号：US13372135
申请日：2012-02-13
CPC分类号： G11C7/00 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C2211/5621
摘要： The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
摘要翻译： 诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。 在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。 如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。 该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。
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公开(公告)号：US08743641B2
公开(公告)日：2014-06-03
申请号：US13227249
申请日：2011-09-07
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/14 , G11C11/5642 , G11C2211/5634
摘要： A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory element states, particularly so as to minimize the affect of temperature variations on reading and sensing states.
摘要翻译： 一种存储元件，其中存储单元的温度系数基本上与参考单元的温度系数相匹配，并且调节存储单元的温度系数以与参考单元的温度系数基本一致，提供了读取或读取存储器的精度提高 特别是为了最小化温度变化对读取和感测状态的影响。
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公开(公告)号：US08589716B2
公开(公告)日：2013-11-19
申请号：US13596953
申请日：2012-08-28
CPC分类号： H03K19/018528 , G05F3/02 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , H03K19/0175 , H03L5/00
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译： 集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。 改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。
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公开(公告)号：US20130208544A1
公开(公告)日：2013-08-15
申请号：US13370833
申请日：2012-02-10
摘要： The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.
摘要翻译： 提供具有读追踪时钟及其方法的闪速存储器的配置。 所提出的闪速存储器包括第一和第二存储电容器，提供流过第一存储电容器的第一电流的第一电流源，提供流过第二存储电容器的第二电流的第二电流源，以及电连接到 第一和第二电流源，并且当第二电流大于第一电流时发出指示正在完成的显影时间的信号。
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公开(公告)号：US20130148445A1
公开(公告)日：2013-06-13
申请号：US13713829
申请日：2012-12-13
摘要： A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.
摘要翻译： 公开了具有字线驱动器和控制电路的存储器电路。 多个字线驱动器耦合到多个字线。 字线驱动器包括可以具有输入和输出的CMOS反相器，以及p型晶体管和n型晶体管。 CMOS反相器的输出耦合到多个字线之一。 控制电路具有多种模式，包括至少第一模式，以经由诸如至少第一晶体管类型的CMOS反相器的第一放电路径放电多个字线的特定字线; 以及第二模式，用于经由诸如至少第二晶体管类型的CMOS反相器的第二放电路径放电多个字线的特定字线。
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公开(公告)号：US08295086B2
公开(公告)日：2012-10-23
申请号：US13180854
申请日：2011-07-12
申请人： Chih-He Chiang , Chung-Kuang Chen , Han-Sung Chen
发明人： Chih-He Chiang , Chung-Kuang Chen , Han-Sung Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/26
摘要： A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.
摘要翻译： 示出了存储器阵列，包括具有源极和漏极掺杂区域的存储器单元，以及经由选择晶体管耦合到掺杂区域的全局位线。 选择晶体管的连接被配置为使得分别耦合到要读取的存储器单元的源极和漏极的两个全局位线的相应负载电容不随着要读取的存储器单元而变化。
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10.发明申请公开(公告)号：US20120265923A1
公开(公告)日：2012-10-18
申请号：US13086988
申请日：2011-04-14
申请人： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
发明人： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
摘要： A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
摘要翻译： 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。
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