公开(公告)号：US06353236B1

公开(公告)日：2002-03-05

申请号：US09396733

申请日：1999-09-15

申请人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

发明人： Tsutomu Yatsuo ,  Takayuki Iwasaki ,  Hidekatsu Onose ,  Shin Kimura

IPC分类号： H01L310312

CPC分类号： H01C7/10 ,  H01C7/12 ,  H01L29/8605 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49431

摘要： A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

摘要翻译： 应用宽带隙半导体单晶作为半导体浪涌吸收体的半导体衬底材料，通过pn结穿透来设置浪涌吸收操作启动电压，以获得具有重复操作和高浪涌的半导体浪涌吸收器 耐力。

公开(公告)号：US06169672A

公开(公告)日：2001-01-02

申请号：US09202924

申请日：1998-12-23

申请人： Shin Kimura ,  Tsutomu Yatsuo ,  Takayuki Iwasaki

发明人： Shin Kimura ,  Tsutomu Yatsuo ,  Takayuki Iwasaki

IPC分类号： H02H7122

CPC分类号： H02M1/34 ,  H02M7/519 ,  H02M2001/344 ,  H02M2001/346 ,  H03K17/08144 ,  Y02B70/1483 ,  Y02B70/1491

摘要： A power converting apparatus comprising a group of semiconductor switches and DC terminals electrically connected to the group of semiconductor switches, in which a clamping circuit is connected to the semiconductor switches or the DC terminals. Otherwise, a diode having a wide band gap is connected in parallel with a snubber diode or a snubber capacitor of a snubber circuit connected in parallel with the semiconductor switches. With such arrangement, an overvoltage or oscillating voltage impressed on the semiconductor switches is suppressed.

摘要翻译： 一种电力转换装置，包括电连接到半导体开关组的半导体开关和DC端子组，其中钳位电路连接到半导体开关或DC端子。 否则，具有宽带隙的二极管与与半导体开关并联连接的缓冲电路的缓冲二极管或缓冲电容器并联连接。 通过这种布置，抑制了对半导体开关施加的过电压或振荡电压。

公开(公告)号：US06180959B2

公开(公告)日：2001-01-30

申请号：US09061145

申请日：1998-04-16

申请人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

发明人： Takayuki Iwasaki ,  Toshiyuki Ohno ,  Tsutomu Yatsuo

IPC分类号： H01L29161

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7722 ,  H03K17/687

摘要： In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source region is not required, and the gate withstand voltage can be highly increased since the substrate is made of silicon carbide, which improves the yield of static induction transistors.

摘要翻译： 在碳化硅静电感应晶体管中，在半导体衬底的表面部分，形成与n型源极区域部分重叠的p型栅极区域，由此栅极区域与源极区域之间的高精度对准 并且栅极耐受电压可以高度增加，因为衬底由碳化硅制成，这提高了静电感应晶体管的产量。

公开(公告)号：US20050006649A1

公开(公告)日：2005-01-13

申请号：US10824442

申请日：2004-04-15

申请人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

发明人： Takayuki Iwasaki ,  Tsutomu Yatsuo ,  Hidekatsu Onose ,  Toshiyuki Oono

IPC分类号： H01L29/772 ,  H02M7/00 ,  H01L31/0312

CPC分类号： H02M7/003 ,  H01L29/7722

摘要： A static induction transistor includes a semiconductor substrate with an energy band gap greater than that of silicon, and the semiconductor substrate has a first gate region to which a gate electrode is connected; and a second gate region positioned within a first semiconductor region which becomes a drain region, and the first gate region is in contact with a second semiconductor region which becomes a source region. According to this construction, the OFF characteristics of the static induction transistor are improved.

摘要翻译： 静电感应晶体管包括具有比硅的能带隙大的能带隙的半导体衬底，并且半导体衬底具有连接有栅电极的第一栅极区域; 以及位于成为漏极区域的第一半导体区域内的第二栅极区域，并且第一栅极区域与成为源极区域的第二半导体区域接触。 根据该结构，能够提高静电感应晶体管的OFF特性。

公开(公告)号：US06384428B1

公开(公告)日：2002-05-07

申请号：US09646305

申请日：2000-09-15

申请人： Toshiyuki Oono ,  Takayuki Iwasaki ,  Tsutomu Yatsuo

发明人： Toshiyuki Oono ,  Takayuki Iwasaki ,  Tsutomu Yatsuo

IPC分类号： H01L310312

CPC分类号： H01L29/7395 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

摘要： The present semiconductor switching device comprises a silicon carbide single crystal of hexagonal symmetry having a first conductive type and a semiconductor region of a second conductive type opposite to the first conductive type and locating in the silicon carbide single crystal. The silicon carbide single crystal of the first conductive type and the semiconductor region of the seconductive type form a pn junction. The pn junction interface has an interface extended in the depth direction from the surface of the silicon carbide single crystal, and the interface includes a crystal plane in parallel to the orientation of the silicon carbide single crystal or approximately in parallel thereto, thereby reducing the leak current.

摘要翻译： 本半导体开关器件包括具有第一导电类型的六边形对称的碳化硅单晶和与第一导电类型相反并且位于碳化硅单晶中的第二导电类型的半导体区域。 第一导电类型的碳化硅单晶和第二导电类型的半导体区域形成pn结。 pn结界面具有从碳化硅单晶的表面沿深度方向延伸的界面，并且界面包括平行于碳化硅单晶的<1120>取向的晶体平面，或者大致与其平行。 减少漏电流。

公开(公告)号：US4651189A

公开(公告)日：1987-03-17

申请号：US680837

申请日：1984-12-12

申请人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Yukimasa Sato ,  Shin Kimura ,  Hiroshi Fukui

发明人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Yukimasa Sato ,  Shin Kimura ,  Hiroshi Fukui

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/32 ,  H01L29/423 ,  H01L29/744 ,  H01L29/74

CPC分类号： H01L29/744 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1004 ,  H01L29/102 ,  H01L29/167 ,  H01L29/32 ,  H01L29/42304 ,  H01L29/42308

摘要： A gate turn-off thyristor and a transistor are disclosed, each of which comprises: a semiconductor substrate including at least three semiconductor layers between a pair of principal surfaces, adjacent ones of the semiconductor layers being different in conductivity type from each other, a first one of the semiconductor layers being formed of at least one strip-shaped region with a constant width, a second one of the semiconductor layers being exposed to a first principal surface of the semiconductor substrate together with the strip-shaped region; a first main electrode kept in ohmic contact with the strip-shaped region at the first principal surface; a first control electrode kept in ohmic contact with the second semiconductor layer on one side of the strip-shaped region in the direction of the width thereof and connected directly to a control terminal; a second control electrode kept in ohmic contact with the second semiconductor layer on the other side of the strip-shaped region in the direction of the width thereof and connected to the control terminal through the first control electrode and the resistance of the second semiconductor layer between the first control electrode and the second control electrode; a second main electrode kept in ohmic contact with a second principal surface of the semiconductor substrate; and means provided in the semiconductor substrate for accelerating the spatial biasing of a conductive region to the other side of the strip-shaped region in the direction of the width thereof when a current flowing across the semiconductor substrate is cut off, thereby enlarging the area of safety operation.

摘要翻译： 公开了一种栅极截止晶闸管和晶体管，每个晶体管包括：半导体衬底，其在一对主表面之间包括至少三个半导体层，相邻的半导体层之间的导电类型彼此不同，第一 一个半导体层由至少一个具有恒定宽度的条形区域形成，第二个半导体层与条形区域一起暴露于半导体衬底的第一主表面; 第一主电极与第一主表面处的带状区域欧姆接触; 第一控制电极在带状区域的宽度方向上与第二半导体层保持欧姆接触，并直接连接到控制端子; 第二控制电极在带状区域的另一侧沿其宽度方向与第二半导体层欧姆接触，并且通过第一控制电极连接到控制端子，并且第二控制电极与第二半导体层之间的电阻 所述第一控制电极和所述第二控制电极; 与所述半导体衬底的第二主表面保持欧姆接触的第二主电极; 以及设置在半导体衬底中的装置，用于当切断流过半导体衬底的电流时，在导电区域的宽度方向上将导电区域的空间偏置加速到带状区域的另一侧，从而扩大 安全运行。

公开(公告)号：US4646122A

公开(公告)日：1987-02-24

申请号：US585606

申请日：1984-03-02

申请人： Shin Kimura ,  Hiroshi Fukui ,  Hisao Amano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Takahiro Nagano

发明人： Shin Kimura ,  Hiroshi Fukui ,  Hisao Amano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Takahiro Nagano

IPC分类号： H01L29/423 ,  H01L29/74

CPC分类号： H01L29/42304 ,  H01L29/42308

摘要： A semiconductor device such as a transistor or gate turn-off thyristor provided with a control electrode for improving the current cut-off performance, is disclosed in which an emitter layer of a semiconductor substrate is formed of a plurality of strip-shaped regions, a base layer adjacent to the strip-shaped regions is exposed to one principal surface of the semiconductor substrate together with the strip-shaped regions, one main electrode is provided on each strip-shaped region, first and second control electrodes are provided on the base layer, on one and the other sides of each strip-shaped region viewed in the direction of the width thereof, respectively, the other main electrode is provided on the second principal surface of the semiconductor substrate, and a gate terminal is not connected to the first control electrode but connected to the second control electrode, in order to draw out carriers unequally by the first and second control electrodes at a turn-off period. At the initial stage of turn-off action, carriers are drawn out mainly by the second control terminal, and a conductive region contracts so as to be limited to the first control electrode side. At the final stage of turn-off action, carriers are drawn out considerably by the first control electrode, to complete the turn-off action.

摘要翻译： 公开了一种半导体器件，例如晶体管或栅极截止晶闸管，其设置有用于提高电流截止性能的控制电极，其中半导体衬底的发射极层由多个条形区域形成， 与带状区域相邻的基底层与条状区域一起暴露于半导体衬底的一个主表面，在每个条形区域上设置一个主电极，在基底层上设置第一和第二控制电极 在从宽度方向观察的每个条形区域的一侧和另一侧上分别设置在该半导体衬底的第二主表面上，另一个主电极没有连接到第一 控制电极，但是连接到第二控制电极，以便在关断周期期间由第一和第二控制电极不相等地引出载流子。 在关断动作的初始阶段，主要由第二控制端子引出载体，并且导电区域收缩以限于第一控制电极侧。 在关断动作的最后阶段，载体被第一控制电极显着地拉出，以完成关断动作。

公开(公告)号：US20090173949A1

公开(公告)日：2009-07-09

申请号：US12281391

申请日：2006-12-27

申请人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

发明人： Tsutomu Yatsuo ,  Shinsuke Harada ,  Kenji Fukuda ,  Mitsuo Okamoto

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/8213 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7806

摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.

摘要翻译： 本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。 该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型 沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成 表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

公开(公告)号：US20090072244A1

公开(公告)日：2009-03-19

申请号：US12281902

申请日：2007-01-16

申请人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

发明人： Shinsuke Harada ,  Makoto Katou ,  Kenji Fukuda ,  Tsutomu Yatsuo

IPC分类号： H01L29/24 ,  H01L21/44

CPC分类号： H01L21/31658 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/324 ,  Y10S438/931

摘要： The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

摘要翻译： 本发明的目的是提供一种用于制造半导体器件的方法，该半导体器件为了形成这种欧姆接触的目的而进行了退火处理，以能够降低欧姆接触电阻并且提供在碳化硅的（000-1）面上， 绝缘膜并提供半导体器件。 制造碳化硅半导体器件的方法包括以下步骤：在至少包含氧和水分的气体中在碳化硅半导体的（000-1）面上进行热氧化，从而以这种方式形成绝缘膜 为了接触碳化硅半导体的（000-1）面，除去绝缘膜的一部分，从而在其中形成开口部，在开口部的至少一部分上沉积接触金属，进行热处理，从而形成 接触金属和碳化硅的反应层，其中热处理在惰性气体和氢气的混合气体中实施。

公开(公告)号：US20080203400A1

公开(公告)日：2008-08-28

申请号：US12025445

申请日：2008-02-04

申请人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

发明人： Kenji Fukuda ,  Junji Senzaki ,  Shinsuke Harada ,  Makoto Kato ,  Tsutomu Yatsuo ,  Mitsuo Okamoto

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

摘要翻译： 提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。 通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。 制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极 区域，清洁半导体区域表面。 在800℃至1150℃的温度下，在含有1％或更多的H 2 O（水）蒸气的气氛中形成栅极绝缘层，以降低界面陷阱密度 栅极绝缘层和半导体区域之间的界面。