NONVOLATILE STORAGE ELEMENT AND METHOD OF MANUFACTURING THEREOF
    3.
    发明申请
    NONVOLATILE STORAGE ELEMENT AND METHOD OF MANUFACTURING THEREOF 有权
    非易失存储元件及其制造方法

    公开(公告)号:US20140024197A1

    公开(公告)日:2014-01-23

    申请号:US14110163

    申请日:2012-04-11

    IPC分类号: H01L45/00

    摘要: A method of manufacturing a variable resistance nonvolatile memory element includes: forming a lower electrode layer above a substrate; forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide; forming an upper electrode layer on the variable resistance layer; and forming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask, wherein in the etching, at least the variable resistance layer is etched using an etching gas containing bromine.

    摘要翻译: 一种制造可变电阻非易失性存储元件的方法包括:在衬底上形成下电极层; 在下电极层上形成包含缺氧过渡金属氧化物的可变电阻层; 在所述可变电阻层上形成上电极层; 以及在所述上电极层上形成图案化掩模,并使用所述图案掩模蚀刻所述上电极层,所述可变电阻层和所述下电极层,其中在所述蚀刻中,至少所述可变电阻层使用含有 溴。

    Molded Hook and Loop Fastener
    4.
    发明申请
    Molded Hook and Loop Fastener 有权
    成型钩环紧固件

    公开(公告)号:US20130340214A1

    公开(公告)日:2013-12-26

    申请号:US14002773

    申请日:2011-03-07

    IPC分类号: A44B18/00

    摘要: The molded hook and loop fastener comprises multiple hook and loop fastener parts on which multiple engaging elements are disposed, and a connection member for connecting the hook and loop fastener parts. The hook and loop fastener parts comprise fixing parts which fix the connection member to backings. The backings comprise forward and rearward extensions that extend in the longitudinal direction from the positions where the fixing parts are disposed. The dimension in the longitudinal direction of the connection member at a connection part is set to be longer than the minimum interval between adjacent hook and loop fastener parts, thereby allowing the molded hook and loop fastener to be bent easily in the width direction, and allowing the forward and rearward extensions to prevent foam resin material from directly hitting the lateral walls.

    摘要翻译: 模制的钩和环紧固件包括多个钩环紧固件部件,多个接合元件设置在该钩环部件上,以及用于连接钩环部件的连接部件。 钩和环紧固件部件包括将连接件固定到背衬上的固定部件。 背衬包括从设置有固定部件的位置沿纵向方向延伸的前后延伸部。 连接部件的连接部件的长度方向的尺寸被设定为比相邻的钩环部件之间的最小间隔长,从而允许成型的钩环紧固件在宽度方向上容易弯曲,并且允许 向前和向后延伸以防止泡沫树脂材料直接撞击侧壁。

    Molded male surface fastener
    5.
    发明授权
    Molded male surface fastener 有权
    模制的阳表面紧固件

    公开(公告)号:US08512845B2

    公开(公告)日:2013-08-20

    申请号:US13124879

    申请日:2008-11-06

    IPC分类号: A44B18/00

    摘要: A molded male surface fastener includes resin invasion preventing walls, which prevent an invasion of a molding foamable resin material of a cushion body, on right and left edge portions along a longitudinal direction of a surface of a flat base member made of a thermoplastic resin, a plurality of engaging elements provided between left and right resin invasion preventing walls, and a linear sealing body that is continuously disposed in the longitudinal direction of the base member along a peripheral portion of a top portion of each resin invasion preventing wall. When an engaging element forming surface of the surface fastener is placed on a concavo-convex surface of foaming body molding cavities of a foaming mold, if the mold has the same magnetic force as that in the related art, the linear sealing body is well adhered along the concavo-convex surface.

    摘要翻译: 模制的阳表面紧固件包括树脂侵入防止壁,其防止沿着由热塑性树脂制成的扁平基底的表面的纵向的左右边缘部分侵入缓冲体的模制发泡树脂材料, 设置在左右树脂防侵入壁之间的多个接合元件,以及沿着每个树脂侵入防止壁的顶部的周边部分沿基体的纵向方向连续设置的线性密封体。 当表面紧固件的接合元件形成表面放置在发泡模具的发泡体模制腔的凹凸表面上时,如果模具具有与现有技术相同的磁力,则线密封体良好地粘附 沿着凹凸表面。

    Method for manufacturing semiconductor device
    8.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US07324866B2

    公开(公告)日:2008-01-29

    申请号:US11305074

    申请日:2005-12-19

    申请人: Shinichi Imai

    发明人: Shinichi Imai

    IPC分类号: G06F19/00

    摘要: A method for manufacturing a semiconductor device is provided in which it is possible to perform process control taking account of wafer information and to deal with the process control in which a recipe is change from one wafer to another. The method comprises steps of inserting a process control system into the path of a network where a manufacturing execution system (MES) and a manufacturing apparatus are connected with each other by using a LAN, obtaining a process result on the lot of the wafers at a previous step through the use of the process control system to rewrite the process recipe, and transmitting the rewritten process recipe from the process control system to the manufacturing apparatus. Since the method includes the step of obtaining the process result on the lot effected at the previous step as wafer information, it is possible to calculate a control parameter taking account of the state of the wafers. Also, since a process control (APC) system is inserted between the MES and the apparatus, there is no communication between the MES and the APC system, so that a communication burden is reduced, thereby the process control can be performed from one wafer to another.

    摘要翻译: 提供一种制造半导体器件的方法,其中可以考虑晶片信息进行处理控制,并且处理其中配方从一个晶片改变到另一个晶片的处理控制。 该方法包括以下步骤:通过使用LAN将制造执行系统(MES)和制造装置彼此连接的网络的路径插入到步骤S中,从而获得晶片批次的处理结果 上一步通过使用过程控制系统重写过程配方,并将重写过程配方从过程控制系统传送到制造设备。 由于该方法包括以上述步骤获得作为晶片信息的批次的处理结果的步骤,因此可以考虑晶片的状态来计算控制参数。 另外,由于在MES和装置之间插入了过程控制(APC)系统,所以在MES和APC系统之间不存在通信,从而减少了通信负担,从而可以从一个晶片到 另一个。

    Pattern inspection apparatus
    9.
    发明申请
    Pattern inspection apparatus 有权
    图案检验仪

    公开(公告)号:US20070064223A1

    公开(公告)日:2007-03-22

    申请号:US11299848

    申请日:2005-12-13

    申请人: Shinichi Imai

    发明人: Shinichi Imai

    IPC分类号: G01N21/00

    摘要: A pattern inspection apparatus is disclosed, which includes a first laser light source for emission of first laser light having a first wavelength, a second laser light source for emission of second laser light having a second wavelength, and a deep ultraviolet (DUV) light source for emission of DUV light with a wavelength of less than or equal to 266 nm based on the first laser light and the second laser light. A first optical fiber is provided for connecting between the first laser light source and the DUV light source. A second optical fiber is for connection between the second laser light source and the DUV light source. The apparatus also includes a pattern inspection unit with the DUV light source being built therein, for inspecting a workpiece pattern being tested by using the DUV light as illumination light therefor.

    摘要翻译: 公开了一种图案检查装置,其包括用于发射具有第一波长的第一激光的第一激光光源,用于发射具有第二波长的第二激光的第二激光源和深紫外(DUV)光源 用于基于第一激光和第二激光发射波长小于或等于266nm的DUV光。 提供第一光纤用于连接第一激光光源和DUV光源。 第二光纤用于第二激光光源和DUV光源之间的连接。 该装置还包括内置有DUV光源的图形检查单元,用于通过使用DUV光作为照明光检查被测试的工件图案。

    Semiconductor device and method for producing the same
    10.
    发明申请
    Semiconductor device and method for producing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US20050156211A1

    公开(公告)日:2005-07-21

    申请号:US11074693

    申请日:2005-03-09

    申请人: Shinichi Imai

    发明人: Shinichi Imai

    摘要: A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and is in contact with the isolating region; an upper electrode provided on the capacitance insulating film so as to be spaced away from the isolating region; an electrode pad provided on the isolating region; a lead conductive film provided over a part of the capacitance insulating film and a part of the isolating region for connecting the upper electrode and the electrode pad; and an interlayer insulating film provided over the substrate. Connection holes penetrating the interlayer insulating film to reach the electrode pad are formed, and the ratio (S/L) of the total sum (S) of exposed areas of the electrode pad in the contact holes with respect to the total sum (L) of lengths of the boundary line in an overlapping portion of the boundary line and the lead conductive films is adjusted such that the breakdown ratio of the capacitance insulating film is substantially zero, the boundary line being between the capacitance insulating film and the isolating region.

    摘要翻译: 本发明的半导体器件包括:半导体衬底,包括有源区和设置成包围有源区的隔离区; 电容绝缘膜,其设置在所述有源区上并与所述隔离区域接触; 设置在电容绝缘膜上以与隔离区隔开的上电极; 设置在所述隔离区域上的电极焊盘; 设置在电容绝缘膜的一部分上的引线导电膜和用于连接上部电极和电极焊盘的隔离区域的一部分; 以及设置在基板上的层间绝缘膜。 形成穿过层间绝缘膜到达电极焊盘的连接孔,并且接触孔中的电极焊盘的暴露区域的总和(S)相对于总和(L)的比(S / L) 在边界线和引线导电膜的重叠部分中的边界线的长度被调节为使得电容绝缘膜的击穿比基本为零,边界线在电容绝缘膜和隔离区之间。