公开(公告)号：US06683491B2

公开(公告)日：2004-01-27

申请号：US10106107

申请日：2002-03-27

申请人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

发明人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

IPC分类号： G05F110

CPC分类号： G11C11/4074 ,  G11C2207/2227

摘要： First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.

摘要翻译： 第一和第二电压发生器产生分别提供给第一内部电源线和第二内部电源电压的第一内部电源电压以供给第二内部电源线。 当第一和第二电压发生器的操作被暂停时，短路使第一和第二内部电源线短路。 第一和第二内部电源线变为浮动，并且各个内部电源线中存储的电荷逐渐排出。 这里，由于电荷被重新分配给两个内部电源线，所以第一和第二内部电源电压随着它们的下降而变得相等。 因此，可以防止第一和第二内部电源电压反转，并且可以防止连接到第一和第二内部电源线的内部电路发生故障。

公开(公告)号：US07032142B2

公开(公告)日：2006-04-18

申请号：US10271533

申请日：2002-10-17

申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara ,  Toru Koga ,  Katsuhiro Mori

发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara ,  Toru Koga ,  Katsuhiro Mori

IPC分类号： G11C29/00 ,  G11C7/00 ,  G06F11/00

CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C2211/4062

摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

公开(公告)号：US20130220846A1

公开(公告)日：2013-08-29

申请号：US13581673

申请日：2012-02-28

申请人： Takao Hiraoka ,  Shuta Nakanami ,  Toru Koga

发明人： Takao Hiraoka ,  Shuta Nakanami ,  Toru Koga

IPC分类号： A61M35/00 ,  B32B37/24 ,  B32B37/12 ,  B65D81/00

CPC分类号： A61K9/7084 ,  A61K31/27 ,  B32B37/1284 ,  B32B37/144 ,  B32B2309/02 ,  B32B2333/08 ,  B32B2333/12 ,  B32B2405/00 ,  B32B2535/00 ,  B65B5/04

摘要： A transdermal patch for the treatment of Alzheimer's disease includes: a backing, a rivastigmine-containing layer, a pressure-sensitive adhesive layer, and a release liner. In the transdermal patch, the rivastigmine-containing layer contains rivastigmine and an alkyl (meth)acrylate resin, the pressure-sensitive adhesive layer is composed of an acrylic pressure-sensitive adhesive containing a (meth)acrylic acid ester having a hydroxy group, and neither the rivastigmine-containing layer nor the pressure-sensitive adhesive layer contains an anti-oxidizing agent.

摘要翻译： 用于治疗阿尔茨海默氏病的透皮贴剂包括：背衬，含有伐他斯他明的层，压敏粘合剂层和剥离衬垫。 在透皮贴剂中，含有伐罗斯的明和（甲基）丙烯酸烷基酯树脂，该压敏粘合剂层由含有具有羟基的（甲基）丙烯酸酯的丙烯酸系压敏粘合剂构成， 利伐斯的明含有层和压敏粘合剂层都不含有抗氧化剂。

公开(公告)号：US20070082771A1

公开(公告)日：2007-04-12

申请号：US11540518

申请日：2006-10-02

申请人： Tetsuya Izumi ,  Hironori Nihei ,  Seonjae Kim ,  Takeshi Chibahara ,  Toru Koga

发明人： Tetsuya Izumi ,  Hironori Nihei ,  Seonjae Kim ,  Takeshi Chibahara ,  Toru Koga

IPC分类号： F16H61/00 ,  F16H59/00

CPC分类号： F16H61/66272 ,  F16H2061/0087 ,  F16H2061/66277 ,  Y10T477/6197 ,  Y10T477/624

摘要： When a line pressure PL serving as a source pressure of a primary pulley (2) and a secondary pulley (3) is controlled on the basis of a control deviation ΔStep, which is the deviation between a step count StepMdl of a step motor (27) corresponding to a target speed ratio I (o) and a value obtained by adding a target deviation GTstep and a starting learned value Gstep to a step count Bstep of the step motor (27) corresponding to an actual speed ratio ip, the engine torque varies dramatically beyond the range of a predetermined value T1 and a predetermined value T2 during a predetermined time period t1, a learning error determination relating to the starting learned value Gstep is prohibited for a predetermined time period t2.

摘要翻译： 基于作为步进电动机（27）的步进计数StepMd1之间的偏差的控制偏差DeltaStep来控制用作初级带轮（2）和次级带轮（3）的源压力的管路压力PL ）和通过将目标偏差GTstep和起始学习值Gstep相加而成的值与对应于实际速度比ip的步进电动机（27）的步数计数Bstep所得到的值，发动机转矩 在预定时间段t 1期间显着地超出预定值T 1和预定值T 2的范围，与开始学习值Gstep有关的学习错误确定被禁止预定时间段t 2。

公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。

公开(公告)号：US08871245B2

公开(公告)日：2014-10-28

申请号：US13581673

申请日：2012-02-28

申请人： Takao Hiraoka ,  Shuta Nakanami ,  Toru Koga

发明人： Takao Hiraoka ,  Shuta Nakanami ,  Toru Koga

IPC分类号： A61F13/00 ,  A61K9/14 ,  A61K31/27

CPC分类号： A61K9/7084 ,  A61K31/27 ,  B32B37/1284 ,  B32B37/144 ,  B32B2309/02 ,  B32B2333/08 ,  B32B2333/12 ,  B32B2405/00 ,  B32B2535/00 ,  B65B5/04

摘要： A transdermal patch for the treatment of Alzheimer's disease includes: a backing, a rivastigmine-containing layer, a pressure-sensitive adhesive layer, and a release liner. In the transdermal patch, the rivastigmine-containing layer contains rivastigmine and an alkyl (meth)acrylate resin, the pressure-sensitive adhesive layer is composed of an acrylic pressure-sensitive adhesive containing a (meth)acrylic acid ester having a hydroxy group, and neither the rivastigmine-containing layer nor the pressure-sensitive adhesive layer contains an anti-oxidizing agent.

摘要翻译： 用于治疗阿尔茨海默氏病的透皮贴片包括：背衬，含有伐他斯他明的层，压敏粘合剂层和剥离衬垫。 在透皮贴剂中，含有伐罗斯的明和（甲基）丙烯酸烷基酯树脂，该压敏粘合剂层由含有具有羟基的（甲基）丙烯酸酯的丙烯酸系压敏粘合剂构成， 利伐斯的明含有层和压敏粘合剂层都不含有抗氧化剂。

公开(公告)号：US06252269B1

公开(公告)日：2001-06-26

申请号：US09422860

申请日：1999-10-25

申请人： Masatomo Hasegawa ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii

发明人： Masatomo Hasegawa ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii

IPC分类号： H01L27108

CPC分类号： H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/105 ,  H01L27/10897

摘要： According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

摘要翻译： 根据本发明的一个方面的半导体存储器，在形成在P型半导体衬底的表面的P型第一阱区域中形成存储单元晶体管，并且将反向偏置电压施加到 P型第一阱区和P型衬底。 此外，通过注入高能N型杂质形成N型逆行区域，从而通过采用N型逆行区域形成较深的N型第二阱区域。 此外，在N型第二阱区中形成P型第三阱区，并且还在其中形成P型发射极区。 因此，P型发射极区域，N型第二阱区域和P型第三阱区域一起构成横向PNP晶体管。 此外，为作为集电极区域的P型第三阱区域保持接地电压。

公开(公告)号：US06229363B1

公开(公告)日：2001-05-08

申请号：US09224354

申请日：1999-01-04

申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： H03L708

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

摘要翻译： 具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。 具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时， 第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

公开(公告)号：US6115284A

公开(公告)日：2000-09-05

申请号：US317902

申请日：1999-05-25

申请人： Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.ds of the cell transistor from being zero by setting the writing voltage (fourth voltage) for H level of the cell capacitor to be lower than the voltage for H level (second voltage) of the bit line, thus reducing a time of writing or re-writing data. Additionally, a pre-charge voltage (first voltage) of the bit lines is set to be lower than the half of the amplitude of the bit line. Thereby, it also becomes possible to prevent the very small voltage of the bit line from being smaller according to the lowered H level voltage in the memory cell.

摘要翻译： 本发明涉及包括由连接到位和字线的单元晶体管形成的存储单元和单元电容器的存储器件。 存储装置包括用于将位线预充电到第一电压的预充电电路，用于检测位线的电压并将位线驱动为用于H电平的第二电压或L电平的第三电压的读出放大器，以及 用于驱动字线以使单元电容器的H电平的写入电压低于低于第二电压的第四电压的字线驱动电路。 本发明的特征在于，第一电压低于第二和第三电压之间的中间值。 根据本发明，通过将单元电容器的H电平的写入电压（第四电压）设定为低于H电平（第二电压）的电压，可以防止单元晶体管的电压Vds为零， 的位线，从而减少写入或重写数据的时间。 此外，位线的预充电电压（第一电压）被设置为低于位线的幅度的一半。 因此，根据存储单元中的低电平电平，也可以防止位线的非常小的电压变小。