公开(公告)号：US20090179281A1

公开(公告)日：2009-07-16

申请号：US12322604

申请日：2009-02-04

申请人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chungxiang Zhu ,  Dim-Lee Kwong

发明人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chungxiang Zhu ,  Dim-Lee Kwong

IPC分类号： H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/7839

摘要： An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.

摘要翻译： 描述了使用镱硅化物（YbSi2-x）作为源极和漏极的N型肖特基势垒源极/漏极晶体管（N-SSDT）。 该结构包括合适的覆盖层堆叠。

公开(公告)号：US20090163005A1

公开(公告)日：2009-06-25

申请号：US12322932

申请日：2009-02-09

申请人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

发明人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

IPC分类号： H01L21/28

CPC分类号： H01L21/28518 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/7839

摘要： A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

摘要翻译： 提出了一种制造用于源极和漏极的镱硅化物（YbSi2-x）的N型肖特基势垒源极/漏极晶体管（N-SSDT）的方法。 YbSi2-x的制造与正常的CMOS工艺兼容，但是不需要ErSi2-x制造所需的超高真空。 为了防止在原位退火过程中镱的氧化并提高膜质量，已经开发了合适​​的覆盖层叠层。

公开(公告)号：US07504328B2

公开(公告)日：2009-03-17

申请号：US11126031

申请日：2005-05-10

申请人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

发明人： Shiyang Zhu ,  Jingde Chen ,  Sungjoo Lee ,  Ming Fu Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

IPC分类号： H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/7839

摘要： A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

摘要翻译： 提出了一种制造用于源极和漏极的镱硅化物（YbSi2-x）的N型肖特基势垒源极/漏极晶体管（N-SSDT）的方法。 YbSi2-x的制造与正常的CMOS工艺兼容，但是不需要ErSi2-x制造所需的超高真空。 为了防止在原位退火过程中镱的氧化并提高膜质量，已经开发了合适​​的覆盖层叠层。

公开(公告)号：US20050275033A1

公开(公告)日：2005-12-15

申请号：US11126031

申请日：2005-05-10

申请人： Shiyang Zhu ,  Jingde Chen ,  Sung Lee ,  Ming Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

发明人： Shiyang Zhu ,  Jingde Chen ,  Sung Lee ,  Ming Li ,  Jagar Singh ,  Chunxiang Zhu ,  Dim-Lee Kwong

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/7839

摘要： A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

摘要翻译： 提出了一种用于源极和漏极制造具有镱硅化物（YbSi 2-x-x）的N型肖特基势垒源极/漏极晶体管（N-SSDT）的方法。 YbSi 2-x 的制造与正常的CMOS工艺兼容，但是在这里不需要对于ErSi 2-x N制造所需的超高真空。 为了防止在原位退火过程中镱的氧化并提高膜质量，已经开发了合适​​的覆盖层叠层。

公开(公告)号：US07002175B1

公开(公告)日：2006-02-21

申请号：US10961355

申请日：2004-10-08

申请人： Jagar Singh ,  Yong Tian Hou ,  Ming Fu Li

发明人： Jagar Singh ,  Yong Tian Hou ,  Ming Fu Li

IPC分类号： H01L29/06

CPC分类号： H01L29/882 ,  B82Y10/00 ,  H01L29/66219

摘要： A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.

摘要翻译： 通过金属对金属热压接合，阳极接合，共晶接合，等离子体接合，硅 - 二极管等工艺，形成双层势垒共振隧道二极管（RTD）并与CMOS / BJT / SiGe器件和电路集成， 硅键合，二氧化硅键合，氮化硅键合和聚合物键合或等离子体键合。 电连接使用在接合过程中对准的导电互连来制成。 所得到的电路具有三维结构。 RTD的隧道势垒层由高K电介质材料形成，例如SiO 2，Si 3 N 4 N 4，Al 2 O 3， 2个O 3，3个O 3，3个O 2，3个O 3， TiO 2，TiO 2，HfO 2，Pr 2 O 3，ZrO 2，N 2， >或其合金和层压体，具有比形成量子阱的材料（包括Si，Ge或SiGe）更高的带隙。 RTD的固有的快速操作速度与减少互连延迟的3-D集成架构相结合，将产生具有低噪声特性的超快速电路。

公开(公告)号：US08476684B2

公开(公告)日：2013-07-02

申请号：US12893794

申请日：2010-09-29

申请人： Edward John Coyne ,  Paul Malachy Daly ,  Jagar Singh ,  Seamus Whiston ,  Patrick Martin McGuinness ,  William Allan Lane

发明人： Edward John Coyne ,  Paul Malachy Daly ,  Jagar Singh ,  Seamus Whiston ,  Patrick Martin McGuinness ,  William Allan Lane

IPC分类号： H01L29/76 ,  H01L21/335

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.

摘要翻译： 具有改进的击穿电压的晶体管及其形成方法在此提供。 在一个实施例中，形成晶体管的方法包括以下步骤：通过掺杂具有第一掺杂剂类型的半导体形成漏极和源极以形成第一类型的半导体，所述漏极和源极彼此分离，其中 漏极包括与第二漏极区相邻的第一掺杂剂浓度的第一漏极区域，使得第二漏极区域的至少一部分位于第一漏极区域和源极之间，并且还包括通过掺杂半导体形成中间区域 以便形成位于漏极和源极之间的第二类型的中间区域，该中间区域与第二漏极区域间隔开。

公开(公告)号：US20120074493A1

公开(公告)日：2012-03-29

申请号：US12893794

申请日：2010-09-29

申请人： Edward John Coyne ,  Paul Malachy Daly ,  Jagar Singh ,  Seamus Whiston ,  Patrick Martin McGuinness ,  William Allan Lane

发明人： Edward John Coyne ,  Paul Malachy Daly ,  Jagar Singh ,  Seamus Whiston ,  Patrick Martin McGuinness ,  William Allan Lane

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.

摘要翻译： 具有改进的击穿电压的晶体管及其形成方法在此提供。 在一个实施例中，形成晶体管的方法包括以下步骤：通过掺杂具有第一掺杂剂类型的半导体形成漏极和源极以形成第一类型的半导体，所述漏极和源极彼此分离，其中 漏极包括与第二漏极区相邻的第一掺杂剂浓度的第一漏极区域，使得第二漏极区域的至少一部分位于第一漏极区域和源极之间，并且还包括通过掺杂半导体形成中间区域 以便形成位于漏极和源极之间的第二类型的中间区域，该中间区域与第二漏极区域间隔开。

公开(公告)号：US20050056827A1

公开(公告)日：2005-03-17

申请号：US10767275

申请日：2004-01-29

申请人： Ming Li ,  Jagar Singh ,  Yong Hou ,  Narayanan Balasubramanian ,  Fujiang Lin

发明人： Ming Li ,  Jagar Singh ,  Yong Hou ,  Narayanan Balasubramanian ,  Fujiang Lin

IPC分类号： G11C5/14 ,  H01L27/06 ,  H01L29/88 ,  H01L29/06

CPC分类号： B82Y10/00 ,  G11C5/142 ,  H01L27/0629 ,  H01L29/785 ,  H01L29/882

摘要： Three configurations of double barrier resonant tunneling diodes (RTD) are provided along with methods of their fabrication. The tunneling barrier layers of the diode are formed of low band offset dielectric materials and produce a diode with good I-V characteristics including negative differential resistance (NDR) with good peak-to-valley ratios (PVR). Fabrication methods of the RTD start with silicon-on-insulator substrates (SOI), producing silicon quantum wells, and are, therefore, compatible with main stream CMOS technologies such as those applied to SOI double gate transistor fabrication. Alternatively, Ge-on-insulator or SiGe-on-insulator substrates can be used if the quantum well is to be formed of Ge or SiGe. The fabrication methods include the formation of both vertical and horizontal silicon quantum well layers. The vertically formed layer may be oriented so that its vertical sides are in any preferred crystallographic plane, such as the 100 or 110 planes.

摘要翻译： 提供了双重屏障共振隧道二极管（RTD）的三种配置及其制造方法。 二极管的隧道势垒层由低带偏移电介质材料形成，并产生具有良好I-V特性的二极管，包括具有良好峰谷比（PVR）的负差分电阻（NDR）。 RTD的制造方法从绝缘体上硅衬底（SOI）开始，产生硅量子阱，因此与诸如应用于SOI双栅晶体管制造的主流CMOS技术相兼容。 或者，如果量子阱由Ge或SiGe形成，则可以使用绝缘体上的锗或绝缘体上硅衬底。 制造方法包括垂直和水平硅量子阱层的形成。 垂直形成的层可以被定向成使得其垂直边在任何优选的结晶平面中，例如100或110平面。