公开(公告)号：US07960276B2

公开(公告)日：2011-06-14

申请号：US12128713

申请日：2008-05-29

申请人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

发明人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

公开(公告)号：US20080284019A1

公开(公告)日：2008-11-20

申请号：US12128713

申请日：2008-05-29

申请人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Kwong Hon Wong

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

公开(公告)号：US08815734B2

公开(公告)日：2014-08-26

申请号：US13290577

申请日：2011-11-07

申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.

摘要翻译： 使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。 在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。 在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。 在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。 在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

公开(公告)号：US08421228B2

公开(公告)日：2013-04-16

申请号：US13405443

申请日：2012-02-27

申请人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.

摘要翻译： 接触结构和形成接触结构的方法。 该结构包括：与衬底的顶部衬底表面直接物理接触的硅化物层; 基板上的电绝缘层; 和绝缘层内的铝塞。 该铝塞的垂直于顶部基板表面的方向的厚度不超过25纳米。 铝塞从硅化物层的顶表面延伸到绝缘层的顶表面。 铝插塞与硅化物层的顶表面直接物理接触并与硅化物层直接物理接触。 该方法包括：在衬底的顶部衬底表面上直接物理接触形成硅化物层; 在基板上形成电绝缘层; 以及在所述绝缘层内形成所述铝塞。

公开(公告)号：US08183145B2

公开(公告)日：2012-05-22

申请号：US11870551

申请日：2007-10-11

申请人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.

摘要翻译： 方法和结构。 形成接触结构的方法包括将硅化物层沉积到基底上; 在所述硅化物层的第一表面上沉积电绝缘层; 通过延伸到第一表面的绝缘层形成通孔; 沉积覆盖所述通孔的底部和至少一个垂直壁的导电层; 从底部去除导电层; 并且用直接与硅化物层接触的铝填充该通孔。 一种结构包括：设置在基板上的硅化物层; 设置在所述硅化物层上的电绝缘层; 延伸穿过绝缘层并直接接触硅化物层的铝塞; 以及设置在插塞和绝缘层之间的导电层。 还包括其中铝层从硅化物层和沟槽的至少一个侧壁选择性地生长的方法。

公开(公告)号：US20100143649A1

公开(公告)日：2010-06-10

申请号：US12706108

申请日：2010-02-16

申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： B32B3/10

CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

公开(公告)号：US20090111235A1

公开(公告)日：2009-04-30

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US20090096108A1

公开(公告)日：2009-04-16

申请号：US11870551

申请日：2007-10-11

申请人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.

摘要翻译： 方法和结构。 形成接触结构的方法包括将硅化物层沉积到基底上; 在所述硅化物层的第一表面上沉积电绝缘层; 通过延伸到第一表面的绝缘层形成通孔; 沉积覆盖所述通孔的底部和至少一个垂直壁的导电层; 从底部去除导电层; 并且用直接与硅化物层接触的铝填充该通孔。 一种结构包括：设置在基板上的硅化物层; 设置在所述硅化物层上的电绝缘层; 延伸穿过绝缘层并直接接触硅化物层的铝塞; 以及设置在插塞和绝缘层之间的导电层。 还包括其中铝层从硅化物层和沟槽的至少一个侧壁选择性地生长的方法。

公开(公告)号：US20090057818A1

公开(公告)日：2009-03-05

申请号：US11847379

申请日：2007-08-30

申请人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

摘要翻译： 一种电可编程保险丝，包括阴极构件，阳极构件和连接构件，其中所述阴极构件，所述阳极构件和所述连接构件各自包括可操作地定位所述可编程熔丝中的感应电迁移的多种材料中的一种。

公开(公告)号：US20080308801A1

公开(公告)日：2008-12-18

申请号：US12193288

申请日：2008-08-18

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/58

CPC分类号： H01L23/576 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/20 ,  H01L28/40 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。