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    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS
    2.
    发明申请
    CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 失效
    创造不同深度的VIAS和TRENCHES

    公开(公告)号：US20110101538A1

    公开(公告)日：2011-05-05

    申请号：US12610624

    申请日：2009-11-02

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

    摘要翻译： 本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。 该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。 还提供了由此制成的半导体结构。

    INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME
    4.
    发明申请
    INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME 有权
    带有MUSHROOM型氧化物覆盖层的互连结构及其制造方法

    公开(公告)号：US20090278258A1

    公开(公告)日：2009-11-12

    申请号：US12115944

    申请日：2008-05-06

    申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    IPC分类号： H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53295 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.

    摘要翻译： 提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。 电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个 多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征 。 本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在 第一电介质盖58。

    FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES
    7.
    发明申请
    FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES 失效
    形成有保护金属线的空气隙

    公开(公告)号：US20110193230A1

    公开(公告)日：2011-08-11

    申请号：US12700792

    申请日：2010-02-05

    申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

    摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.

    摘要翻译： 提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度 电介质层的表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模可以具有多个随机布置的孔。 每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。 掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。 随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。 可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。 此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

    Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same
    8.
    发明授权
    Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same 有权
    具有蘑菇状氧化物覆盖层的互连结构及其制造方法

    公开(公告)号：US07687877B2

    公开(公告)日：2010-03-30

    申请号：US12115944

    申请日：2008-05-06

    申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    IPC分类号： H01L23/485 ,  H01L21/768

    CPC分类号： H01L23/53295 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.

    摘要翻译： 提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。 电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个 多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征 。 本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在 第一电介质盖58。

    Formation of air gap with protection of metal lines
    10.
    发明授权
    Formation of air gap with protection of metal lines 失效
    形成气隙，保护金属线

    公开(公告)号：US08399350B2

    公开(公告)日：2013-03-19

    申请号：US12700792

    申请日：2010-02-05

    申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

    摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.

    摘要翻译： 一种在其电介质层中具有气隙的微电子元件的制造方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度 高于介电层表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模仅暴露具有较大高度的盖层的第二部分的表面。 随后，蚀刻剂可以被引导到盖层的第一和第二部分。 材料可以从暴露于蚀刻剂的介电层去除。