公开(公告)号：US07064563B2

公开(公告)日：2006-06-20

申请号：US10919686

申请日：2004-08-17

申请人： Shu-Lin Ho ,  Shih-Chieh Wang

发明人： Shu-Lin Ho ,  Shih-Chieh Wang

IPC分类号： G01R27/08

CPC分类号： H05K3/361 ,  G01R27/205 ,  G01R31/046 ,  H05K1/0268 ,  H05K1/117 ,  H05K2203/162

摘要： A structure and a method for measuring the bonding resistance are provided. The structure for measuring a bonding resistance between a first object and a second object is provided, wherein the first object has a plurality of first pins and a reference pin, and the second object has a plurality of second pins corresponding to the plurality of first pins and the reference pin. The structure further includes a first circuit formed by electrically connecting the reference pin to the first pin adjacent to the reference pin in a first direction, and a second circuit formed by electrically connecting a second pin corresponding to the reference pin to the adjacent second pin in a second direction. By connecting the first and the second circuits in series, the value of the bonding resistance is easily measured.

摘要翻译： 提供了一种用于测量接合电阻的结构和方法。 提供了用于测量第一物体和第二物体之间的接合电阻的结构，其中所述第一物体具有多个第一销和参考销，并且所述第二物体具有与所述多个第一销对应的多个第二销 和参考引脚。 该结构还包括第一电路，其通过在第一方向上将参考引脚与参考引脚相邻的第一引脚电连接而形成;以及第二电路，其通过将对应于参考引脚的第二引脚电连接到相邻的第二引脚而形成 第二个方向。 通过串联连接第一和第二电路，可以容易地测量接合电阻的值。

公开(公告)号：US07129718B2

公开(公告)日：2006-10-31

申请号：US11412808

申请日：2006-04-27

申请人： Shu-Lin Ho ,  Shih-Chieh Wang

发明人： Shu-Lin Ho ,  Shih-Chieh Wang

IPC分类号： G01R27/08

CPC分类号： H05K3/361 ,  G01R27/205 ,  G01R31/046 ,  H05K1/0268 ,  H05K1/117 ,  H05K2203/162

摘要： A structure and a method for measuring the bonding resistance are provided. The structure for measuring a bonding resistance between a first object and a second object is provided, wherein the first object has a plurality of first pins and a reference pin, and the second object has a plurality of second pins corresponding to the plurality of first pins and the reference pin. The structure further includes a first circuit formed by electrically connecting the reference pin to the first pin adjacent to the reference pin in a first direction, and a second circuit formed by electrically connecting a second pin corresponding to the reference pin to the adjacent second pin in a second direction. By connecting the first and the second circuits in series, the value of the bonding resistance is easily measured.

公开(公告)号：US20060192572A1

公开(公告)日：2006-08-31

申请号：US11412808

申请日：2006-04-27

申请人： Shu-Lin Ho ,  Shih-Chieh Wang

发明人： Shu-Lin Ho ,  Shih-Chieh Wang

IPC分类号： G01R27/08

CPC分类号： H05K3/361 ,  G01R27/205 ,  G01R31/046 ,  H05K1/0268 ,  H05K1/117 ,  H05K2203/162

摘要： A structure and a method for measuring the bonding resistance are provided. The structure for measuring a bonding resistance between a first object and a second object is provided, wherein the first object has a plurality of first pins and a reference pin, and the second object has a plurality of second pins corresponding to the plurality of first pins and the reference pin. The structure further includes a first circuit formed by electrically connecting the reference pin to the first pin adjacent to the reference pin in a first direction, and a second circuit formed by electrically connecting a second pin corresponding to the reference pin to the adjacent second pin in a second direction. By connecting the first and the second circuits in series, the value of the bonding resistance is easily measured.

公开(公告)号：US20050259096A1

公开(公告)日：2005-11-24

申请号：US10919686

申请日：2004-08-17

申请人： Shu-Lin Ho ,  Shih-Chieh Wang

发明人： Shu-Lin Ho ,  Shih-Chieh Wang

IPC分类号： G01R27/20 ,  G01R31/04 ,  H01L23/495 ,  H05K1/02 ,  H05K1/11 ,  H05K3/36

CPC分类号： H05K3/361 ,  G01R27/205 ,  G01R31/046 ,  H05K1/0268 ,  H05K1/117 ,  H05K2203/162

摘要： A structure and a method for measuring the bonding resistance are provided. The structure for measuring a bonding resistance between a first object and a second object is provided, wherein the first object has a plurality of first pins and a reference pin, and the second object has a plurality of second pins corresponding to the plurality of first pins and the reference pin. The structure further includes a first circuit formed by electrically connecting the reference pin to the first pin adjacent to the reference pin in a first direction, and a second circuit formed by electrically connecting a second pin corresponding to the reference pin to the adjacent second pin in a second direction. By connecting the first and the second circuits in series, the value of the bonding resistance is easily measured.

摘要翻译： 提供了一种用于测量接合电阻的结构和方法。 提供了用于测量第一物体和第二物体之间的接合电阻的结构，其中所述第一物体具有多个第一销和参考销，并且所述第二物体具有与所述多个第一销对应的多个第二销 和参考引脚。 该结构还包括第一电路，其通过在第一方向上将参考引脚与参考引脚相邻的第一引脚电连接而形成;以及第二电路，其通过将对应于参考引脚的第二引脚电连接到相邻的第二引脚而形成 第二个方向。 通过串联连接第一和第二电路，可以容易地测量接合电阻的值。

公开(公告)号：US08444793B2

公开(公告)日：2013-05-21

申请号：US12701615

申请日：2010-02-08

申请人： Hsin-Chang Hsiung ,  Shu-Lin Ho

发明人： Hsin-Chang Hsiung ,  Shu-Lin Ho

IPC分类号： B29C73/04 ,  B29C65/54 ,  B29C63/22 ,  B32B37/06 ,  B32B37/12 ,  B32B38/10 ,  B32B43/00 ,  C08J5/12

CPC分类号： B32B38/1841 ,  B32B37/1284 ,  B32B2037/268 ,  B32B2307/542 ,  B32B2309/105 ,  B32B2457/14 ,  Y10T156/11 ,  Y10T156/1153 ,  Y10T428/31515

摘要： The present invention provides a semiconductor device and a fabricating method thereof. The fabricating method comprises: providing a first substrate; forming a soft dry film having an adhesive film and a release film; sticking the soft dry film on the first substrate with the adhesive film; removing the release film; sticking a second substrate on the adhesive film; and heating the adhesive film to solidify the adhesive film to form a solid adhesive film. The semiconductor device comprises: a first substrate, a solid adhesive film, and a second substrate. The solid adhesive film is formed on the first substrate, and the second substrate is formed on the solid adhesive film.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 制造方法包括：提供第一基板; 形成具有粘合膜和脱模膜的软干膜; 用粘合膜将柔软干膜粘在第一基片上; 去除脱模膜; 在粘合膜上粘贴第二衬底; 并加热粘合剂膜以固化粘合剂膜以形成固体粘合剂膜。 半导体器件包括：第一衬底，固体粘合膜和第二衬底。 固体粘合膜形成在第一基板上，第二基板形成在固体粘合膜上。

公开(公告)号：US20060022340A1

公开(公告)日：2006-02-02

申请号：US10711412

申请日：2004-09-17

申请人： Shu-Lin Ho ,  Pao-Yun Tang

发明人： Shu-Lin Ho ,  Pao-Yun Tang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/013

摘要： An electrical conducting structure including an integrated circuit, a substrate, and a plurality of bumps, wherein at least one bump comprises a first conductive part connected to the integrated circuit at one end; a second conductive part connected to the integrated circuit at one end; a conductive connection part connecting the first conductive part and the second conductive part; a first insulation part surrounding the first conductive part and the second conductive part; and a second insulation part located between the first conductive part and the second conductive part.

摘要翻译： 包括集成电路，基板和多个凸块的导电结构，其中至少一个凸块包括在一端连接到集成电路的第一导电部件; 在一端连接到集成电路的第二导电部件; 连接所述第一导电部和所述第二导电部的导电性连接部; 围绕所述第一导电部和所述第二导电部的第一绝缘部; 以及位于所述第一导电部和所述第二导电部之间的第二绝缘部。

公开(公告)号：US20050270466A1

公开(公告)日：2005-12-08

申请号：US10711617

申请日：2004-09-29

申请人： Pao-Yun Tang ,  Shu-Lin Ho ,  Kei-Hsiung Yang

发明人： Pao-Yun Tang ,  Shu-Lin Ho ,  Kei-Hsiung Yang

IPC分类号： G02F1/1345

CPC分类号： G02F1/1345

摘要： A liquid crystal display module manufactured by a chip-on-glass technology includes at least one glass substrate having a display area and a peripheral area. A plurality of scan and data lines is separately formed on the display area along horizontal and vertical directions. The liquid crystal display module also includes at least one gate driver chip and at least one source driver chip mounted on the peripheral area. The gate and source driver chips transmit signals to the scan and data lines via a plurality of output terminals, and thicknesses of the gate and source driver chips are less than 0.3 mm.

摘要翻译： 通过玻璃技术制造的液晶显示模块包括至少一个具有显示区域和周边区域的玻璃基板。 多个扫描和数据线在水平和垂直方向上分别形成在显示区域上。 液晶显示模块还包括安装在周边区域上的至少一个栅极驱动器芯片和至少一个源极驱动器芯片。 栅极和源极驱动器芯片通过多个输出端子将信号传输到扫描和数据线，并且栅极和源极驱动器芯片的厚度小于0.3mm。

公开(公告)号：US20110195257A1

公开(公告)日：2011-08-11

申请号：US12701615

申请日：2010-02-08

申请人： Hsin-Chang Hsiung ,  Shu-Lin Ho

发明人： Hsin-Chang Hsiung ,  Shu-Lin Ho

IPC分类号： B32B27/38 ,  B32B38/10 ,  H01L21/50

CPC分类号： B32B38/1841 ,  B32B37/1284 ,  B32B2037/268 ,  B32B2307/542 ,  B32B2309/105 ,  B32B2457/14 ,  Y10T156/11 ,  Y10T156/1153 ,  Y10T428/31515

摘要： The present invention provides a semiconductor device and a fabricating method thereof. The fabricating method comprises: providing a first substrate; forming a soft dry film having an adhesive film and a release film; sticking the soft dry film on the first substrate with the adhesive film; removing the release film; sticking a second substrate on the adhesive film; and heating the adhesive film to solidify the adhesive film to form a solid adhesive film. The semiconductor device comprises: a first substrate, a solid adhesive film, and a second substrate. The solid adhesive film is formed on the first substrate, and the second substrate is formed on the solid adhesive film.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 制造方法包括：提供第一基板; 形成具有粘合膜和脱模膜的软干膜; 用粘合膜将柔软干膜粘在第一基片上; 去除脱模膜; 在粘合膜上粘贴第二衬底; 并加热粘合剂膜以固化粘合剂膜以形成固体粘合剂膜。 半导体器件包括：第一衬底，固体粘合膜和第二衬底。 固体粘合膜形成在第一基板上，第二基板形成在固体粘合膜上。

公开(公告)号：US06995474B1

公开(公告)日：2006-02-07

申请号：US10711412

申请日：2004-09-17

申请人： Shu-Lin Ho ,  Pao-Yun Tang

发明人： Shu-Lin Ho ,  Pao-Yun Tang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/013

摘要： An electrical conducting structure including an integrated circuit, a substrate, and a plurality of bumps, wherein at least one bump comprises a first conductive part connected to the integrated circuit at one end; a second conductive part connected to the integrated circuit at one end; a conductive connection part connecting the first conductive part and the second conductive part; a first insulation part surrounding the first conductive part and the second conductive part; and a second insulation part located between the first conductive part and the second conductive part.

摘要翻译： 包括集成电路，基板和多个凸块的导电结构，其中至少一个凸块包括在一端连接到集成电路的第一导电部件; 在一端连接到集成电路的第二导电部件; 连接所述第一导电部和所述第二导电部的导电性连接部; 围绕所述第一导电部和所述第二导电部的第一绝缘部; 以及位于所述第一导电部和所述第二导电部之间的第二绝缘部。

公开(公告)号：US20060175711A1

公开(公告)日：2006-08-10

申请号：US11054693

申请日：2005-02-08

申请人： Pao-Yun Tang ,  Shu-Lin Ho ,  Hsiu-Sheng Hsu ,  Nan-Cheng Huang

发明人： Pao-Yun Tang ,  Shu-Lin Ho ,  Hsiu-Sheng Hsu ,  Nan-Cheng Huang

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/05076 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/90 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for bonding an IC chip to a substrate where the method comprises the steps of providing an IC chip with a plurality of bumps each having a buffer layer and a conductive layer, providing a substrate having a plurality of conductive elements arranged corresponding to the plurality of bumps, placing a non-conductive film between the plurality of conductive devices and their corresponding bumps, and pressing and heating the IC chip and the substrate so that the plurality of bumps are in contact with the plurality of conductive elements respectively. The bonding structure is formed between a first and second substrate where the structure has a buffer layer having an opening and formed on the first substrate, a conductive layer formed on the buffer layer, and a non-conductive film formed between the conductive layer and the second substrate as a bonding medium for the bonding structure.

摘要翻译： 一种用于将IC芯片接合到基板的方法，其中所述方法包括以下步骤：提供具有缓冲层和导电层的多个凸块的IC芯片，提供具有对应于多个布置的多个导电元件的基板 在多个导电器件及其对应的凸块之间放置非导电膜，并且对IC芯片和衬底进行加压和加热，使得多个凸块分别与多个导电元件接触。 接合结构形成在第一和第二基板之间，其中结构具有开口并形成在第一基板上的缓冲层，形成在缓冲层上的导电层，以及形成在导电层和导电层之间的非导电膜 第二基板作为接合结构的接合介质。