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    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07554186B2

    公开(公告)日：2009-06-30

    申请号：US12110682

    申请日：2008-04-28

    申请人： Mamoru Kudo ,  Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Mamoru Kudo ,  Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： H01L23/50

    CPC分类号： H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/1041 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

    摘要： A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

    摘要翻译： 半导体器件包括第一半导体封装，第二半导体封装。 第一半导体封装包括其中形成有第一腔的第一半导体封装基座，安装在第一腔中的第一安装部件和设置在第一半导体封装基座上的第一磁体。 第二半导体封装包括第二半导体封装基座，其具有形成在其中的第二腔，安装在第二腔中的第二安装构件和设置在第二半导体封装基座上以吸附第一磁体的第二磁体。 第一半导体封装和第二半导体封装通过第一磁体和第二磁体之间的磁力的吸附而被堆叠。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080315386A1

    公开(公告)日：2008-12-25

    申请号：US12110682

    申请日：2008-04-28

    申请人： Mamoru KUDO ,  Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Mamoru KUDO ,  Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： H01L23/50

    CPC分类号： H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/1041 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

    摘要： A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

    摘要翻译： 半导体器件包括第一半导体封装，第二半导体封装。 第一半导体封装包括其中形成有第一腔的第一半导体封装基座，安装在第一腔中的第一安装部件和设置在第一半导体封装基座上的第一磁体。 第二半导体封装包括第二半导体封装基座，其具有形成在其中的第二腔，安装在第二腔中的第二安装构件和设置在第二半导体封装基座上以吸附第一磁体的第二磁体。 第一半导体封装和第二半导体封装通过第一磁体和第二磁体之间的磁力的吸附而被堆叠。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07012831B2

    公开(公告)日：2006-03-14

    申请号：US10749559

    申请日：2004-01-02

    申请人： Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： G11C11/24

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4076

    摘要： A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, and consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.

    摘要翻译： 一种用于在保持写入数据的可信度的同时实现高速写入的半导体存储器件，其中在存储单元阵列的位线和输入/输出数据线之间提供写入门，当选择的字线 成为激活状态，并且根据写数据设置到输入/输出数据线的写入信号在写入时经由写入门被施加到所选择的位线，使得可以在之后立即执行到所选择的存储器单元的写入 在写入时激活所选择的字线，并且可以与未选择的存储单元的读取和刷新并行地执行对所选择的存储器单元的写入，因此可以充分确保用于存储对所选存储单元的电荷的时间和写入 可以实现高速度。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07027347B2

    公开(公告)日：2006-04-11

    申请号：US10749510

    申请日：2004-01-02

    申请人： Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： G11C8/00

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4096 ,  G11C2207/2245

    摘要： A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an address register for holding a write address, a data register for holding write data, an address matching detection circuit for detecting whether an address held in the address register matches with an address input this time, and when reading is performed continuously from writing on the same address of the same memory bank, reading is not performed on a memory cell specified by a read address and data held in the data register is output as read data, so that memory accessing made continuously to the same address can be performed at a high speed.

    摘要翻译： 一种半导体存储器件，用于改善共享数据总线的利用率和数据传输速率，并且在不增加控制电路规模的情况下实现高速数据访问，其中多存储体DRAM具有提供有存储器 用于保持写入地址的地址寄存器，用于保持写入数据的数据寄存器，用于检测保持在地址寄存器中的地址是否与此时输入的地址一致的地址匹配检测电路， 相同存储体的相同地址，读取不是由读取地址指定的存储单元执行，数据寄存器中保存的数据作为读取数据输出，从而能够以高位执行对连续地进行相同地址的存储器访问 速度。