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1.发明授权公开(公告)号：US08293594B2
公开(公告)日：2012-10-23
申请号：US12835907
申请日：2010-07-14
IPC分类号： H01L21/84
CPC分类号： H01L27/1225 , H01L27/124 , H01L29/45
摘要： An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.
摘要翻译： 目的是提高半导体器件的开口率。 半导体器件包括驱动器电路部分和在同一衬底上的显示部分（也称为像素部分）。 驱动器电路包括用于驱动电路的通道蚀刻薄膜晶体管和使用金属形成的驱动电路布线。 用于驱动电路的薄膜晶体管的源极和漏极由金属形成。 使用氧化物半导体形成用于驱动电路的薄膜晶体管的沟道层。 显示部分包括用于像素的底接触薄膜晶体管和使用氧化物导体形成的显示部分布线。 用于像素的薄膜晶体管的源极和漏极电极层使用氧化物导体形成。 使用氧化物半导体形成用于像素的薄膜晶体管的半导体层。
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公开(公告)号：US08643018B2
公开(公告)日：2014-02-04
申请号：US13616019
申请日：2012-09-14
CPC分类号： H01L27/1225 , H01L27/124 , H01L29/45
摘要： An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.
摘要翻译： 目的是提高半导体器件的开口率。 半导体器件包括驱动器电路部分和在同一衬底上的显示部分（也称为像素部分）。 驱动器电路包括用于驱动电路的通道蚀刻薄膜晶体管和使用金属形成的驱动电路布线。 用于驱动电路的薄膜晶体管的源极和漏极由金属形成。 使用氧化物半导体形成用于驱动电路的薄膜晶体管的沟道层。 显示部分包括用于像素的底接触薄膜晶体管和使用氧化物导体形成的显示部分布线。 用于像素的薄膜晶体管的源极和漏极电极层使用氧化物导体形成。 使用氧化物半导体形成用于像素的薄膜晶体管的半导体层。
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公开(公告)号：US08816349B2
公开(公告)日：2014-08-26
申请号：US12898357
申请日：2010-10-05
申请人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Junpei Sugao , Hideki Uochi , Yasuo Nakamura
发明人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Junpei Sugao , Hideki Uochi , Yasuo Nakamura
IPC分类号： H01L27/14
CPC分类号： H01L29/7869 , H01L21/02164 , H01L21/0217 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/324 , H01L21/76801 , H01L21/76828 , H01L21/76838 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/42384 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78606
摘要： By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
摘要翻译： 通过使用包含Cu的导电层作为长引线，可以抑制布线电阻的增加。 此外，包括Cu的导电层以与形成TFT的沟道区域的氧化物半导体层不重叠并被包括氮化硅的绝缘层包围的方式设置，由此Cu的扩散可以 防止 因此，可以制造高度可靠的半导体器件。 具体地说，作为半导体装置的一个实施方式的显示装置，即使在尺寸或定义增加的情况下也能够具有高的显示质量，并且稳定地工作。
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公开(公告)号：US08344374B2
公开(公告)日：2013-01-01
申请号：US12898366
申请日：2010-10-05
申请人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Yasuo Nakamura , Junpei Sugao , Hideki Uochi
发明人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Yasuo Nakamura , Junpei Sugao , Hideki Uochi
IPC分类号： H01L29/10
CPC分类号： H01L29/78669 , H01L27/1214 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78606 , H01L29/78678 , H01L29/7869
摘要： It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
摘要翻译： 本发明的目的是提供一种由具有良好的显示质量的显示装置代表的半导体器件，其中在半导体层和电极之间的连接部分中产生的寄生电阻被抑制，并且具有诸如电压降等的不利影响 防止由于布线电阻而导致像素的信号布线，灰度级的缺陷等。 为了实现上述目的，根据本发明的半导体器件可以具有这样的结构，其中具有低电阻的布线连接到薄膜晶体管，其中包括具有高氧亲和力的金属的源电极和漏电极是 连接到具有抑制的杂质浓度的氧化物半导体层。 另外，包含氧化物半导体的薄膜晶体管也可以被要被密封的绝缘膜包围。
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公开(公告)号：US07989815B2
公开(公告)日：2011-08-02
申请号：US12571552
申请日：2009-10-01
申请人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
发明人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
IPC分类号： H01L29/04
CPC分类号： H01L29/7869 , H01L27/0266 , H01L27/1225 , H01L27/124
摘要： The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.
摘要翻译： 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 第一布线层和第二布线层，其在栅极绝缘膜上方并且其端部与栅电极重叠; 以及氧化物半导体层，其在所述栅电极的上方并与所述栅极绝缘膜和所述第一布线层和所述第二布线层的端部接触。 非线性元件的栅电极和扫描线或信号线包括在布线中，非线性元件的第一或第二布线层直接连接到布线，以施加栅极的电位 电极。
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公开(公告)号：US20110084268A1
公开(公告)日：2011-04-14
申请号：US12898366
申请日：2010-10-05
申请人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Yasuo Nakamura , Junpei Sugao , Hideki Uochi
发明人： Shunpei Yamazaki , Jun Koyama , Masahiro Takahashi , Hideyuki Kishida , Akiharu Miyanaga , Yasuo Nakamura , Junpei Sugao , Hideki Uochi
CPC分类号： H01L29/78669 , H01L27/1214 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78606 , H01L29/78678 , H01L29/7869
摘要： It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
摘要翻译： 本发明的目的是提供一种由具有良好的显示质量的显示装置代表的半导体器件，其中在半导体层和电极之间的连接部分中产生的寄生电阻被抑制，并且具有诸如电压降等的不利影响 防止由于布线电阻而导致像素的信号布线，灰度级的缺陷等。 为了实现上述目的，根据本发明的半导体器件可以具有这样的结构，其中具有低电阻的布线连接到薄膜晶体管，其中包括具有高氧亲和力的金属的源电极和漏电极是 连接到具有抑制的杂质浓度的氧化物半导体层。 另外，包含氧化物半导体的薄膜晶体管也可以被要被密封的绝缘膜包围。
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公开(公告)号：US6110770A
公开(公告)日：2000-08-29
申请号：US229306
申请日：1999-01-13
IPC分类号： H01L21/20 , H01L21/00 , H01L21/324 , H01L21/336 , H01L27/12 , H01L29/02 , H01L29/78 , H01L29/786 , H01L21/84
CPC分类号： H01L21/2022 , H01L27/1281 , H01L29/66757
摘要： A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20 to 150.degree. C.
摘要翻译： 一种通过在不高于非晶硅的结晶温度的温度下进行退火将基本无定形态的硅膜结晶化的半导体制造方法，其包括在表面上或非晶硅膜下选择性地形成涂层 ，含有镍，铁，钴，铂或钯的颗粒，簇等作为纯金属或其化合物，例如硅化物，盐等，成形为岛状部分，线状部分，条纹 ，或点; 然后在低于非晶硅的结晶温度的温度下将所得结构退火20〜150℃。
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公开(公告)号：US5956579A
公开(公告)日：1999-09-21
申请号：US893361
申请日：1997-07-15
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L21/2022 , H01L21/2026 , H01L27/1277 , H01L29/66757 , H01L29/78618
摘要： Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.
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公开(公告)号：US5650338A
公开(公告)日：1997-07-22
申请号：US216277
申请日：1994-03-23
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L27/1214 , H01L29/66757
摘要： In film forming of thin film semiconductors (TFTs), a gate electrode having an anodic-oxidizable material is formed on a substrate, and the surface of the gate electrode is oxidized by anodic oxidation in an electrolytic solution so that the surface of the gate electrode is coated with an insulating film. The doping is performed using the gate electrode and the anodic oxide film as a mask, to form a source and a drain region. Then, when the laminate is again dipped in an electrolytic solution, and a voltage is applied to the gate electrode so that a current curing produces in the laminate. During the current curing, a positive voltage is preferably applied to the gate electrode for N-channel TFTs and a negative voltage is preferably to the gate electrode for P-channel TFTs. After the doping, the source and the drain region is activated by laser annealing or the like, prior to the current curing.
摘要翻译： 在薄膜半导体（TFT）的成膜中，在基板上形成具有阳极氧化材料的栅电极，并且通过电解液中的阳极氧化使栅电极的表面氧化，使得栅电极的表面 涂有绝缘膜。 使用栅电极和阳极氧化膜作为掩模进行掺杂，以形成源区和漏区。 然后，当层叠体再次浸渍在电解液中时，向栅电极施加电压，使得层压体产生电流固化。 在电流固化期间，优选对N沟道TFT的栅电极施加正电压，对P沟道TFT优选施加负电压。 在掺杂之后，在目前的固化之前，源极和漏极区域被激光退火等激活。
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公开(公告)号：US09196633B2
公开(公告)日：2015-11-24
申请号：US12556704
申请日：2009-09-10
申请人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
发明人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
IPC分类号： H01L33/00 , H01L27/12 , G02F1/1362 , H01L27/02 , H01L29/786
CPC分类号： H01L27/124 , G02F1/136204 , G02F1/136286 , H01L27/0266 , H01L27/1225 , H01L29/7869
摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅极绝缘层上的栅电极重叠的第一氧化物半导体层，以及第一布线层和第二布线层 其端部与第一氧化物半导体层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。
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