公开(公告)号：US20070053360A1

公开(公告)日：2007-03-08

申请号：US11488005

申请日：2006-07-18

申请人： Shunsuke Hino ,  Toshio Doi ,  Motoyuki Unno

发明人： Shunsuke Hino ,  Toshio Doi ,  Motoyuki Unno

IPC分类号： H04L12/56

CPC分类号： H04L12/10 ,  H04L41/08 ,  H04L43/0876 ,  H04L43/16

摘要： There is provided a network connection apparatus including a plurality of line connection parts 201 connected to network lines 111 to transmit and receive packets, a transmission destination decision part 104 for deciding a transmission destination on the basis of header information of packet received by a first one of the plurality of line connection parts, a packet transfer part 103 for transferring packets to a second line connection destination corresponding to the transmission destination decided by the transmission destination decision part, a power supply part 102 for supplying power to the line connection parts and a power control part 203 for controlling supply of power to each of the line connection parts from the power supply part.

摘要翻译： 提供了一种网络连接装置，包括连接到网络线111以发送和接收分组的多个线路连接部分201，用于基于由第一个分组接收的分组的报头信息来确定发送目的地的发送目的地判定部分104 多个线路连接部分的分组传送部分103，用于将分组传送到与由发送目的地决定部分确定的发送目的地相对应的第二线路连接目的地的分组传送部分103，用于向线路连接部分供电的电源部分102 功率控制部203，用于控制从电源部向每个线路连接部供电。

公开(公告)号：US07839878B2

公开(公告)日：2010-11-23

申请号：US11488005

申请日：2006-07-18

申请人： Shunsuke Hino ,  Toshio Doi ,  Motoyuki Unno

发明人： Shunsuke Hino ,  Toshio Doi ,  Motoyuki Unno

IPC分类号： H04L12/28 ,  H04L12/26 ,  H04L12/50

CPC分类号： H04L12/10 ,  H04L41/08 ,  H04L43/0876 ,  H04L43/16

摘要： A network connection apparatus including: a plurality of line connection parts connected to network lines to transmit and receive packets; a transmission destination decision part for deciding a transmission destination on the basis of header information of a packet received by a first one of the plurality of line connection parts; a packet transfer part for transferring packets to a second line connection destination corresponding to the transmission destination decided by the transmission destination decision part; and, a power supply part for supplying power to the line connection parts and a power control part for controlling supply of power to each of the line connection parts from the power supply part.

摘要翻译： 一种网络连接装置，包括：多个线路连接部分，连接到网络线路以发送和接收分组; 发送目的地决定部，根据由所述多个线路连接部中的第一个接收到的分组的头部信息来决定发送目的地; 分组传送部分，用于将分组传送到与由传输目的地决定部分确定的发送目的地相对应的第二线路连接目的地; 以及用于向线路连接部分供电的电源部分和用于控制从电源部分到每个线路连接部分的电力供应的功率控制部分。

公开(公告)号：US20100003245A1

公开(公告)日：2010-01-07

申请号：US12374473

申请日：2007-07-19

申请人： Toshio Doi ,  Hideharu Abe ,  Naoshi Fukushima ,  Hitoshi Tai ,  Takakazu Mizuno ,  Masahiko Kinosaki

发明人： Toshio Doi ,  Hideharu Abe ,  Naoshi Fukushima ,  Hitoshi Tai ,  Takakazu Mizuno ,  Masahiko Kinosaki

IPC分类号： A61K39/395 ,  C12N5/06 ,  C07K16/18

CPC分类号： C07K16/22 ,  A61K2039/505 ,  C07K2317/76

摘要： When an anti-human BMP antibody was added to cells of an immortalized human mesangial cell line cultured in the presence of human BMP, the anti-human BMP antibody significantly suppressed the production of type IV collagen in mesangial cells. A number of signaling pathways are involved in abnormal proliferation of type IV collagen. It was therefore completely unpredictable whether merely blocking the BMP signal would indeed suppress the abnormal proliferation of type IV collagen. However, for the first time, the present inventors demonstrated that anti-BMP antibodies are very effective in suppressing the abnormal proliferation of type IV collagen. Thus, anti-BMP antibodies can be used as novel therapeutic agents for kidney diseases associated with abnormal proliferation of the mesangial matrix.

摘要翻译： 当将抗人BMP抗体加入到在人BMP存在下培养的永生化人肾小球系膜细胞的细胞中时，抗人BMP抗体显着抑制肾小球系膜细胞中IV型胶原的产生。 许多信号通路涉及IV型胶原异常增殖。 因此，完全不可预测的是，只是阻断BMP信号将确实抑制IV型胶原蛋白的异常增殖。 然而，本发明人第一次证明抗BMP抗体在抑制IV型胶原蛋白的异常增殖方面非常有效。 因此，抗BMP抗体可用作与肾小球系膜基质异常增殖相关的肾脏疾病的新型治疗剂。

公开(公告)号：US5956520A

公开(公告)日：1999-09-21

申请号：US710902

申请日：1996-09-24

申请人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

发明人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

IPC分类号： G06F9/30 ,  G06F11/22 ,  G06F11/28 ,  G06F12/08 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F13/4213

摘要： An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

摘要翻译： 外部总线I / F部分具有这样的功能，其中当由指令执行部分请求总线访问时，由CPU产生的逻辑地址的高位数位从输出端子输出到芯片的外部 作为用于指示由当前执行的程序访问的集成ROM空间，集成RAM空间和外部空间中的哪一个的空间标识符。 使用由CPU生成的地址的一部分，使得当前执行的程序访问的空间从外部实时获知，而不需要外部硬件。

公开(公告)号：US5737589A

公开(公告)日：1998-04-07

申请号：US308346

申请日：1994-09-19

申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

CPC分类号： H04L7/02

摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。

公开(公告)号：US5544340A

公开(公告)日：1996-08-06

申请号：US362755

申请日：1994-12-22

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

IPC分类号： G06F12/08

CPC分类号： G06F12/0886

摘要： A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

摘要翻译： 一种控制设置在CPU和主存储器之间的高速缓冲存储器的方法，其中将要写入高速缓冲存储器的数据和地址对存储在缓冲存储器中。 处理从缓冲存储器读取的多对数据和地址，以比较其地址字段。 基于比较的结果，确定了将数据写入高速缓冲存储器中的写入控制，其被细分为多个存储体。 结果，将多对数据和地址写入高速缓冲存储器的多个组，各对的地址彼此不同。 通过上述规定，可以对高速缓冲存储器的每一组独立地进行写入操作，从而提高写入吞吐量。

公开(公告)号：US5526509A

公开(公告)日：1996-06-11

申请号：US386757

申请日：1995-02-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

公开(公告)号：US5065048A

公开(公告)日：1991-11-12

申请号：US397199

申请日：1989-08-23

申请人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Mitsuo Asai ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： H03K19/003 ,  H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/00338

摘要： A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

摘要翻译： 一种动态半导体逻辑电路，包括：MOS FET逻辑部分，用于响应输入模式预充电之后的输入逻辑信号和所述逻辑部分的内部节点进行高速逻辑运算; CMOS / BiCMOS输出缓冲器部分，用于输出 逻辑运算，以及噪声抑制部，用于防止误操作而不牺牲高速运行特性。 该电路采用0.5μm规则技术制造，并且在4.5 V或更低的低压电源下以高速运行，具有预充电部分，用于对MOS FET逻辑部分的输出节点和内部节点进行预充电 以及噪声抑制部分，用于通过反馈输出缓冲器部分的输出来将逻辑部分的输出节点锁存到源极电位，以便放大软误差容限。 闭锁电流保持在小于预定比率以保持高速操作特性。

公开(公告)号：US20160333412A1

公开(公告)日：2016-11-17

申请号：US15146515

申请日：2016-05-04

申请人： Toshio Doi ,  HUBIT GENOMIX INC.

发明人： Toshio Doi ,  Hideharu ABE

IPC分类号： C12Q1/68 ,  C07K16/28 ,  G01N33/68

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。

公开(公告)号：US20100135988A1

公开(公告)日：2010-06-03

申请号：US12585882

申请日：2009-09-28

申请人： Toshio Doi ,  Hideharu Abe

发明人： Toshio Doi ,  Hideharu Abe

IPC分类号： A61K39/395 ,  C12Q1/00 ,  C12Q1/68 ,  G01N33/53 ,  C12Q1/48 ,  G01N33/561 ,  A61K31/7088

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。