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14 条记录 (耗时 0.017 秒)

    Multiprocessor system including a docking system
    1.
    发明授权
    Multiprocessor system including a docking system 有权
    多处理器系统包括对接系统

    公开(公告)号：US06438622B1

    公开(公告)日：2002-08-20

    申请号：US09193269

    申请日：1998-11-17

    申请人： Siamack Haghighi ,  Neil W. Songer

    发明人： Siamack Haghighi ,  Neil W. Songer

    IPC分类号： G06F1300

    CPC分类号： G06F1/1632 ,  G06F15/7864

    摘要： A system includes a docking base unit having a first processor and a portable computing device that is dockable to the docking base unit that includes a second processor. A module identifies the number of processors in the system once the portable computing device is docked to the docking base unit and configures the system as a multiprocessor system if more than one processor is identified.

    摘要翻译： 系统包括具有第一处理器和便携式计算设备的对接基座单元，该便携式计算设备可对接到包括第二处理器的对接基座单元。 一旦便携式计算设备对接到对接基座单元，则模块识别系统中的处理器数量，并且如果识别出多于一个的处理器，则将系统配置为多处理器系统。

    Activity alignment algorithm by masking traffic flows
    3.
    发明授权
    Activity alignment algorithm by masking traffic flows 有权
    通过屏蔽流量来进行活动对齐算法

    公开(公告)号：US08650427B2

    公开(公告)日：2014-02-11

    申请号：US13077727

    申请日：2011-03-31

    申请人： William Knolla ,  Douglas R. Moran ,  Neil W. Songer

    发明人： William Knolla ,  Douglas R. Moran ,  Neil W. Songer

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3209

    摘要： Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.

    摘要翻译： 用于从活动对准关闭状态进入状态的活动对准的方法和装置的实施例; 掩蔽在活动对齐状态的至少一部分期间接收的一个或多个业务流; 以及至少部分地基于所述屏蔽所述一个或多个业务流，在所述活动对齐状态之后，在所述活动对齐状态之后，在处于所述活动对准状态至少第一时间段之后进入所述活动对齐关闭状态。 还公开了其它变型和实施方案。

    Method and apparatus for upgrading a computer system
    4.
    发明授权
    Method and apparatus for upgrading a computer system 失效
    用于升级计算机系统的方法和装置

    公开(公告)号：US5983297A

    公开(公告)日：1999-11-09

    申请号：US777410

    申请日：1996-12-30

    申请人： James L. Noble ,  Frank P. Hart ,  Ravi Nagaraj ,  Neil W. Songer

    发明人： James L. Noble ,  Frank P. Hart ,  Ravi Nagaraj ,  Neil W. Songer

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4068

    摘要： A method and apparatus for upgrading a computer system from one processor generation to another processor generation. The processor and its corresponding primary bridge are included together on the same circuit board. The circuit board has an interface which can be inserted into a socket of a system. The interface socket includes the memory bus and peripheral component bus from the bridge.

    摘要翻译： 一种用于将计算机系统从一个处理器生成升级到另一个处理器生成的方法和装置。 处理器及其相应的主桥包含在同一电路板上。 电路板具有可插入系统的插座的接口。 接口插座包括桥接器的存储器总线和外设组件总线。

    Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
    5.
    发明授权
    Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent 失效
    具有耦合到DMA控制器和多个地址线的接口逻辑的输入输出控制器，用于向DMA代理传送控制信息

    公开(公告)号：US5729762A

    公开(公告)日：1998-03-17

    申请号：US426818

    申请日：1995-04-21

    申请人： James P. Kardach ,  Sung-Soo Cho ,  Debra T. Cohen ,  John W. Horigan ,  Neil W. Songer

    发明人： James P. Kardach ,  Sung-Soo Cho ,  Debra T. Cohen ,  John W. Horigan ,  Neil W. Songer

    IPC分类号： G06F13/28 ,  G06F15/40

    CPC分类号： G06F13/28

    摘要： A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.

    摘要翻译： 计算机系统根据DMA传输协议执行直接存储器访问（DMA）传输。 计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 DMA代理，系统存储器和DMA控制器耦合到总线。 DMA控制器使用PCI总线的电接口来控制系统内存和DMA代理之间的DMA传输。 根据一个实施例，系统I / O控制器耦合在DMA控制器和PCI总线之间。 系统I / O控制器使用PCI总线的电接口将DMA控制信息从DMA控制器传送到DMA代理。 PCI总线的电接口包括多个地址线和耦合到DMA代理的授权信号线，其中I / O控制器在断言授权信号线的同时向DMA代理发送DMA控制信息的系统。

    Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
    6.
    发明授权
    Method and apparatus for arbitrating for a bus to enable split transaction bus protocols 失效
    用于仲裁总线以实现拆分事务总线协议的方法和装置

    公开(公告)号：US5621897A

    公开(公告)日：1997-04-15

    申请号：US421114

    申请日：1995-04-13

    申请人： Bechara F. Boury ,  Charles E. Kuhlmann ,  Terence J. Lohman ,  Neil W. Songer ,  Ronald E. Valli

    发明人： Bechara F. Boury ,  Charles E. Kuhlmann ,  Terence J. Lohman ,  Neil W. Songer ,  Ronald E. Valli

    IPC分类号： G06F13/362 ,  G06F13/36

    CPC分类号： G06F13/362

    摘要： An arrangement and method for arbitration to enable split transaction bus protocols provides for a slave to assert a mask signal that sets a mask bit in a mask register when the slave is not ready to complete a requested transaction. A requesting master is forced off the bus and prevented from re-arbitrating while the mask bit is set in the register. When the slave is ready to complete the transaction, a release master signal is asserted which causes the bit in the shift register to be reset. The requesting master is then able to re-arbitrate for use of the bus to complete the transaction. The usable bandwidth of the bus is increased since other masters are able to arbitrate and use the bus until the slave is ready to complete the transaction with the first requesting master.

    摘要翻译： 用于启用拆分事务总线协议的仲裁的布置和方法提供从机在从机未准备好完成所请求的事务时，提供设置掩码寄存器中的掩码位的掩码信号。 请求主机被强制关闭总线，并防止在掩码位置位在寄存器中进行重新仲裁。 当从机准备好完成交易时，断言主信号被断言，这使得移位寄存器中的位被复位。 然后，请求主机能够重新仲裁以使用总线来完成交易。 总线的可用带宽增加，因为其他主机能够仲裁和使用总线，直到从机准备完成与第一请求主机的交易。

    ACTIVITY ALIGNMENT ALGORITHM BY MASKING TRAFFIC FLOWS
    7.
    发明申请
    ACTIVITY ALIGNMENT ALGORITHM BY MASKING TRAFFIC FLOWS 有权
    通过拦截交通流量的活动对齐算法

    公开(公告)号：US20120254644A1

    公开(公告)日：2012-10-04

    申请号：US13077727

    申请日：2011-03-31

    申请人： William Knolla ,  Douglas R. Moran ,  Neil W. Songer

    发明人： William Knolla ,  Douglas R. Moran ,  Neil W. Songer

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3209

    摘要： Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.

    摘要翻译： 用于从活动对准关闭状态进入状态的活动对准的方法和装置的实施例; 掩蔽在活动对齐状态的至少一部分期间接收的一个或多个业务流; 以及至少部分地基于所述屏蔽所述一个或多个业务流，在所述活动对齐状态之后，在所述活动对齐状态之后，在处于所述活动对准状态至少第一时间段之后进入所述活动对齐关闭状态。 还公开了其它变型和实施方案。

    Method and apparatus for providing a processor module for a computer system
    8.
    发明授权
    Method and apparatus for providing a processor module for a computer system 失效
    用于为计算机系统提供处理器模块的方法和装置

    公开(公告)号：US6041372A

    公开(公告)日：2000-03-21

    申请号：US774515

    申请日：1996-12-30

    申请人： Frank P. Hart ,  Ravi Nagaraj ,  James L. Noble ,  Neil W. Songer

    发明人： Frank P. Hart ,  Ravi Nagaraj ,  James L. Noble ,  Neil W. Songer

    IPC分类号： G06F13/40 ,  G06F13/10 ,  H03K5/09

    CPC分类号： G06F13/4068

    摘要： A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.

    摘要翻译： 一种用于在将信号提供给处理器之前将信号从第一电压电平转换为第二电压电平的方法和装置。 电路板包括用于经由插座将电路板耦合到外围子系统的接口。 电路板还包括接收第一电压电平，第一信号线和第二信号线的信号的处理器。 第一信号线耦合到接口，并向指示第一电压电平的外围子系统提供参考信号。 第二信号线还耦合到接口并且在信号已被转换到第一电压电平之后从外围子系统提供子系统信号。

    Controlling Reduced Power States Using Platform Latency Tolerance
    10.
    发明申请
    Controlling Reduced Power States Using Platform Latency Tolerance 有权
    使用平台延迟容限来控制低功耗状态

    公开(公告)号：US20150006923A1

    公开(公告)日：2015-01-01

    申请号：US13927746

    申请日：2013-06-26

    申请人： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

    发明人： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

    摘要： In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。