公开(公告)号：US20120056194A1

公开(公告)日：2012-03-08

申请号：US12876028

申请日：2010-09-03

申请人： Sima Dimitrijev ,  Li Wang ,  Jisheng Han ,  Alan Iacopi ,  Leonie Hold ,  Philip Tanner ,  Fred Kong ,  Herbert Barry Harrison

发明人： Sima Dimitrijev ,  Li Wang ,  Jisheng Han ,  Alan Iacopi ,  Leonie Hold ,  Philip Tanner ,  Fred Kong ,  Herbert Barry Harrison

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L29/94 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/86

摘要： Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form barrier structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate, for fabricating various silicon carbide-based semiconductor devices, including silicon carbide-based memory elements and cells. In some embodiments, a semiconductor wafer includes a silicon substrate, a barrier-seed layer disposed over the silicon substrate, and a silicon carbide layer formed over the barrier-seed layer. The semiconductor wafer can be used to form a variety of SiC-based semiconductor devices. In one embodiment, a silicon carbide-based memory element is formed to include barrier-seed layer, multiple silicon carbide layers formed over the barrier-seed layer, and a dielectric layer formed over the multiple silicon carbide layers.

摘要翻译： 本发明的实施例一般涉及半导体和半导体制造技术，更具体地，涉及用于形成阻挡结构以便于在诸如硅基底层之类的衬底上形成碳化硅外延的器件，集成电路，衬底，晶片和方法 ，用于制造各种基于碳化硅的存储元件和电池的基于碳化硅的半导体器件。 在一些实施例中，半导体晶片包括硅衬底，设置在硅衬底上的阻挡种子层和形成在阻挡种子层上的碳化硅层。 半导体晶片可用于形成各种SiC基半导体器件。 在一个实施例中，形成基于碳化硅的存储元件以包括阻挡种子层，在阻挡种子层上形成的多个碳化硅层以及形成在多个碳化硅层上的电介质层。

公开(公告)号：US20110042686A1

公开(公告)日：2011-02-24

申请号：US12543478

申请日：2009-08-18

申请人： Jisheng Han ,  Sima Dimitrijev ,  Li Wang ,  Philip Tanner ,  Leonie Hold ,  Alan Iacopi ,  Fred Kong ,  Herbert Barry Harrison

发明人： Jisheng Han ,  Sima Dimitrijev ,  Li Wang ,  Philip Tanner ,  Leonie Hold ,  Alan Iacopi ,  Fred Kong ,  Herbert Barry Harrison

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L21/0262 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02529 ,  H01L21/02579

摘要： Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant.

摘要翻译： 本发明的实施例一般涉及半导体和半导体制造技术，更具体地涉及用于形成碳化硅结构的器件，集成电路，衬底和方法，包括掺杂的外延层（例如，P掺杂的碳化硅外延层），由 依次强调硅和碳的供应来源。 在一些实施例中，形成碳化硅外延层的方法可以包括在硅源的存在下沉积层，以及在沉积层之后吹扫气态材料。 此外，该方法可以包括在碳源和掺杂剂的存在下将层转化为碳化硅的子层，并且清除其它气态材料。 在一些实施例中，硅源的存在可以独立于碳源和/或掺杂剂的存在。

公开(公告)号：US20110042685A1

公开(公告)日：2011-02-24

申请号：US12543473

申请日：2009-08-18

申请人： Li Wang ,  Sima Dimitrijev ,  Alan Iacopi ,  Jisheng Han ,  Leonie Hold ,  Philip Tanner ,  Fred Kong ,  Herbert Harrison

发明人： Li Wang ,  Sima Dimitrijev ,  Alan Iacopi ,  Jisheng Han ,  Leonie Hold ,  Philip Tanner ,  Fred Kong ,  Herbert Harrison

IPC分类号： H01L29/24 ,  C30B23/00

CPC分类号： C30B25/165 ,  C30B29/36 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0262

摘要： Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including epitaxial layers, by supplying sources of silicon and carbon with sequential emphasis. In at least some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer on a substrate in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source, and purging other gaseous materials subsequent to converting the layer. The presence of the silicon source can be independent of the presence of the carbon source. In some embodiments, dopants, such as n-type dopants, can be introduced during the formation of the epitaxial layer of silicon carbide.

摘要翻译： 本发明的实施例一般涉及半导体和半导体制造技术，更具体地涉及通过以顺序强调提供硅和碳的源来形成包括外延层的碳化硅结构的器件，集成电路，衬底和方法。 在至少一些实施例中，形成碳化硅外延层的方法可以包括在硅源的存在下在衬底上沉积层，以及在沉积层之后吹扫气态材料。 此外，该方法可以包括在碳源的存在下将层转化为碳化硅的子层，以及在转换层之后吹扫其它气态材料。 硅源的存在可以独立于碳源的存在。 在一些实施例中，可以在形成碳化硅外延层期间引入掺杂剂，例如n型掺杂剂。

公开(公告)号：US07781873B2

公开(公告)日：2010-08-24

申请号：US10424096

申请日：2003-04-28

申请人： Wei H. Koh ,  Fred Kong ,  David Chen

发明人： Wei H. Koh ,  Fred Kong ,  David Chen

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

摘要翻译： 用于组装高性能，高速半导体存储器IC器件的薄型小外形IC引线框塑料封装，例如具有在1千兆赫兹范围内的高数据传输速率的动态随机存取存储器（DRAM）。 封装引线框架通过倒装芯片接合到IC器件或通过插入器的导电（例如焊料）凸块与IC器件输入 - 输出焊盘电互连。 内插器在导电扇出的轨迹的相对端包含整体卷曲的微弹簧触点。 插入器通过带自动接合，焊接或粘合粘合附接到引线框接合焊盘。 通过上述倒装芯片凸块或插入器与IC器件互连的引线框架被封装和修整，以形成作为标准薄小外形封装（TSOP）的鸥翼型周边引线，或作为微型封装引线， 引线框（MLF）封装。

公开(公告)号：US06686656B1

公开(公告)日：2004-02-03

申请号：US10340961

申请日：2003-01-13

申请人： Wei H. Koh ,  Fred Kong ,  Daniel Hsu

发明人： Wei H. Koh ,  Fred Kong ,  Daniel Hsu

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A vertically integrated chip scale package (CSP) assembly comprising two or more single chip package subassemblies having an upper level CSP subassembly superimposed directly above a lower level CSP subassembly. The lower-most CSP subassembly in the vertical stack contains an array of solder balls for interconnection to a printed wiring board. The vertical electrical connection between the upper and lower level package subassemblies is accomplished by using wire bonding from perimeter wire bonding pads located on an upper level substrate extension to matching perimeter wire bonding pads located on a lower level substrate extension that is longer in length than the upper level substrate extension. The stacked package subassemblies are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant for protection. The assembled vertical stack has the appearance of a single CSP but is shorter in height than two individual packages that are stacked together with solder ball interconnects located therebetween.

摘要翻译： 一种垂直集成的芯片级封装（CSP）组件，其包括两个或更多个单芯片封装子组件，其具有直接叠加在较低级CSP子组件上方的上级CSP子组件。 垂直堆叠中最下面的CSP子组件包含用于与印刷线路板互连的焊球阵列。 上层和下层封装子组件之间的垂直电气连接是通过使用位于上层基板延伸部上的周边引线接合焊盘的引线接合来实现的，该匹配周边引线接合焊盘位于下层衬底延伸部上， 上层底层延伸。 堆叠的包装组件通过使用薄的粘合剂材料结合在一起，并且周边引线接合被密封剂封装以进行保护。 组装的垂直堆叠具有单个CSP的外观，但是与位于其间的焊料球互连堆叠在一起的两个单独的封装相比，其高度更短。