专利检索 ap:("Simon J. S. McElrea" OR "Lawrence Douglas Andrews, Jr." OR "Scott McGrath" OR "Terrence Caskey" OR "Scott Jay Crane" OR "Marc E. Robinson" OR "Loreto Cantillep") AND inv:"Marc E. Robinson" 第 1 页

1.

发明授权
Electrically interconnected stacked die assemblies 有权
标题翻译：电互连叠层模组件

公开(公告)号：US08629543B2

公开(公告)日：2014-01-14

申请号：US12913604

申请日：2010-10-27

申请人： Simon J. S. McElrea , Lawrence Douglas Andrews, Jr. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

发明人： Simon J. S. McElrea , Lawrence Douglas Andrews, Jr. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

IPC分类号： H01L23/02

CPC分类号： H01L25/50 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/24011 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48465 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

摘要： In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

摘要翻译： 在堆叠组件配置中，堆叠中的连续裸片在芯片边缘处被偏移，在芯片边缘处设置芯片，并且芯片通过导电迹线互连。在一些实施例中，导电迹线由导电聚合物形成。提供了一种电绝缘保形涂层，其在电连接的管芯焊盘处具有开口。

2.

发明授权
Electrically interconnected stacked die assemblies 有权

公开(公告)号：US08723332B2

公开(公告)日：2014-05-13

申请号：US12124077

申请日：2008-05-20

申请人： Simon J. S. McElrea , Lawrence Douglas Andrews, Jr. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

发明人： Simon J. S. McElrea , Lawrence Douglas Andrews, Jr. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

IPC分类号： H01L23/48

CPC分类号： H01L25/50 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/24011 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48465 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

摘要： In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

3.

发明申请
Electrically Interconnected Stacked Die Assemblies 有权
标题翻译：电连接堆叠模具组件

公开(公告)号：US20110037159A1

公开(公告)日：2011-02-17

申请号：US12913604

申请日：2010-10-27

申请人： Simon J. S. McElrea , Lawrence Douglas Andrews, JR. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

发明人： Simon J. S. McElrea , Lawrence Douglas Andrews, JR. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

IPC分类号： H01L23/52

CPC分类号： H01L25/50 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/24011 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48465 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

摘要： In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

摘要翻译： 在堆叠组件配置中，堆叠中的连续裸片在芯片边缘处被偏移，在芯片边缘处设置芯片，并且芯片通过导电迹线互连。在一些实施例中，导电迹线由导电聚合物形成。提供了一种电绝缘保形涂层，其在电连接的管芯焊盘处具有开口。

4.

发明申请
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES 有权
标题翻译：电气互连堆叠式电池组件

公开(公告)号：US20080303131A1

公开(公告)日：2008-12-11

申请号：US12124077

申请日：2008-05-20

申请人： Simon J.S. McElrea , Lawrence Douglas Andrews, JR. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

发明人： Simon J.S. McElrea , Lawrence Douglas Andrews, JR. , Scott McGrath , Terrence Caskey , Scott Jay Crane , Marc E. Robinson , Loreto Cantillep

IPC分类号： H01L23/02

CPC分类号： H01L25/50 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/24011 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48465 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

摘要： In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

摘要翻译： 在堆叠组件配置中，堆叠中的连续裸片在芯片边缘处被偏移，在芯片边缘处设置芯片，并且芯片通过导电迹线互连。在一些实施例中，导电迹线由导电聚合物形成。提供了一种电绝缘保形涂层，其在电连接的管芯焊盘处具有开口。

5.

发明授权
Semiconductor die mount by conformal die coating 有权
标题翻译：半导体模具安装通过适形模具涂层

公开(公告)号：US08704379B2

公开(公告)日：2014-04-22

申请号：US12199080

申请日：2008-08-27

申请人： Scott Jay Crane , Simon J. S. McElrea , Scott McGrath , Weiping Pan , DeAnn Eileen Melcher , Marc E. Robinson

发明人： Scott Jay Crane , Simon J. S. McElrea , Scott McGrath , Weiping Pan , DeAnn Eileen Melcher , Marc E. Robinson

IPC分类号： H01L23/48

CPC分类号： H01L24/83 , H01L23/293 , H01L23/3171 , H01L23/3185 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/24145 , H01L2224/24146 , H01L2224/27452 , H01L2224/29005 , H01L2224/29006 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83191 , H01L2224/8385 , H01L2224/92247 , H01L2225/0651 , H01L2225/06524 , H01L2225/06551 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01038 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2924/00012

摘要： A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a conformal coating between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on either or both a die attach area of a surface of the die, or a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

摘要翻译： 半导体管芯上的保形涂层提供了管芯和支撑件之间的粘附。不需要额外的粘合剂将模具固定在支撑件上。共形涂层在组装期间保护模具，并且用于使模具与模具可接触的导电部件电绝缘。保形涂层可以是有机聚合物，例如聚对二甲苯。此外，将模具粘附到可任选地是另一个模具的支撑件上的方法包括在模具和支撑件之间提供共形涂层，以及加热模具和支撑件之间的涂层。保形涂层可以设置在模具表面的芯片附接区域或支撑体表面的模具安装区域中的任一个或两者上; 并且可以在将模具放置在支撑件上之后提供保形涂层。

6.

发明申请
CHIP SCALE STACKED DIE PACKAGE 审中-公开
标题翻译：芯片尺码堆叠包装

公开(公告)号：US20090102038A1

公开(公告)日：2009-04-23

申请号：US12251624

申请日：2008-10-15

申请人： SIMON J.S. MCELREA , Marc E. Robinson , Lawrence Douglas Andrews, JR. , Terrence Caskey , Scott McGrath , Yong Du , Al Vindasius

发明人： SIMON J.S. MCELREA , Marc E. Robinson , Lawrence Douglas Andrews, JR. , Terrence Caskey , Scott McGrath , Yong Du , Al Vindasius

IPC分类号： H01L23/488 , H01L21/02

CPC分类号： H01L23/3114 , H01L23/525 , H01L25/0657 , H01L2224/24145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2225/06572

摘要： A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.

摘要翻译： 准备用于堆叠在芯片级堆叠管芯组件中的管芯，其具有从管芯边缘向内的区域中的互连位置和在至少一个管芯边缘附近的互连焊盘。可以通过组件中的第一管芯和支撑件上的电路之间的连接来进行堆叠管芯组件的二次互连; 并且堆叠中的管芯之间的互连可以通过z-互连与在支撑件的管芯附接侧中的接合焊盘附近或在一个或多个管芯边缘处的连接来进行。用于制备模具的方法包括在晶片级或模具阵列级进行到高级阶段的工艺。