摘要:
An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要:
A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.
摘要:
A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.
摘要翻译:实施例电路提供晶体管体偏置电压,使得I ON / OFF与I OFF之间的比率在温度范围内是恒定的,其中I < 是ON时的晶体管电流,当OFF时,I 是晶体管电流(泄漏)。 在一个实施例中,nFET被偏置以将电流镜提供给电流反射镜,该电流镜将节点的当前AI导通,nFET被偏置以提供I < OFF SUB>到从节点吸收当前BI OFF的电流镜,并且放大器从节点向nFET的体式终端提供反馈,使得在稳态AI < ON SUB> = BI SUB>,其中A和B在温度范围内是常数独立的。 以这种方式,在一些温度范围内,比率I ON / OFF / OFF保持在B / A。 描述和要求保护其他实施例。