摘要:
An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要:
A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.
摘要:
A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.