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1.发明授权Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method 有权最大对数映射等价对数似然比生成软维特比架构系统和方法公开(公告)号：US08694877B2
公开(公告)日：2014-04-08
申请号：US12924707
申请日：2010-10-01
IPC分类号： H03M13/03
CPC分类号： H03M13/4146 , G06F11/1076 , G11B20/18 , H03M13/3905 , H03M13/3927 , H03M13/4184 , H03M13/42 , H03M13/6343 , H03M13/6502 , H04L1/0054 , H04L1/0055
摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
摘要翻译： 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。
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2.发明申请Max-log-map equivalence log likelihood ratio generation soft Viterbi architecture system and method 有权最大对数映射等价对数似然比生成软维特比架构系统和方法公开(公告)号：US20110197112A1
公开(公告)日：2011-08-11
申请号：US12924707
申请日：2010-10-01
CPC分类号： H03M13/4146 , G06F11/1076 , G11B20/18 , H03M13/3905 , H03M13/3927 , H03M13/4184 , H03M13/42 , H03M13/6343 , H03M13/6502 , H04L1/0054 , H04L1/0055
摘要： A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
摘要翻译： 修改的软输出维特比算法（SOVA）检测器接收软信息值序列，并为每个软信息值确定最佳路径和备用路径，并且进一步确定当给定软件的最佳和替代路径导致相同值时 信息值，是否存在离开替代路径的第三路径，其导致相对于给定软信息值的最佳路径的相反决定。 然后，SOVA检测器在更新最佳路径的可靠性时考虑第三条路径。 改进的SOVA检测器通过Fossorier方法有效地实现了最大对数映射的等效性，并且包括SOVA检测器的前N个级的修正的可靠性度量单位，其中N是给定路径的存储器深度，并且包括用于 检测器的剩余阶段。
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公开(公告)号：US09021342B2
公开(公告)日：2015-04-28
申请号：US12924658
申请日：2010-10-01
CPC分类号： H03M13/4146 , H03M13/4107
摘要： In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.
摘要翻译： 在一个实施例中，公开了一种操作SOVA系统的系统和方法，其包括确定网格树的开始和停止值，并使用开始和停止值来确定网格树内的多个分支的初始状态。
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公开(公告)号：US20110167322A1
公开(公告)日：2011-07-07
申请号：US12924658
申请日：2010-10-01
CPC分类号： H03M13/4146 , H03M13/4107
摘要： In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.
摘要翻译： 在一个实施例中，公开了一种操作SOVA系统的系统和方法，其包括确定网格树的开始和停止值，并使用开始和停止值来确定网格树内的多个分支的初始状态。
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5.发明申请APPARATUS AND METHOD FOR DETERMINING A READ LEVEL OF A FLASH MEMORY AFTER AN INACTIVE PERIOD OF TIME 有权在时间不活动期后确定闪存存储器的读取级别的装置和方法公开(公告)号：US20120239976A1
公开(公告)日：2012-09-20
申请号：US13179466
申请日：2011-07-08
IPC分类号： G06F11/00
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.
摘要翻译： 公开了一种用于在存储器电路关闭之后确定非易失性存储器电路中的驻留时间的装置和方法。 通过比较读取在关闭之前存储的测试块所需的第一读取电平电压和读取关闭后存储的第二测试块所需的第二读取电平电平来计算电压偏移。 从由电压偏移索引的查找表和编程/擦除周期数确定停机时间。 停留时间是根据驱动器温度，时钟和块时间戳计算的。 一旦计算了停留时间，控制器就部分地基于驻留时间计算新的读取电平电压，并且向存储器电路提供表示新的读取电平电压的一个或多个编程命令以读取存储器电路。
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6.发明授权Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine 有权使用完全可配置存储器，多级流水线逻辑和嵌入式处理器来实现多位特里算法网络搜索引擎的装置和方法公开(公告)号：US07782853B2
公开(公告)日：2010-08-24
申请号：US10313174
申请日：2002-12-06
CPC分类号： H04L45/54
摘要： A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.
摘要翻译： 多位特里网络搜索引擎由对应于最长前缀步长的数量的流水线逻辑单元和用于保存前缀表的一组存储器块来实现。 每个流水线逻辑单元限于一个存储器访问，并且流水线逻辑单元链中的终止点是可变的，以处理不同长度的前缀。 存储器块通过网格交叉开关连接到流水线逻辑单元并形成一组虚拟存储器组，其中任何给定的物理存储器组中的存储器块可被分配给任何特定流水线逻辑单元的虚拟存储体。 嵌入式可编程处理器管理前缀表中的路由插入和删除以及虚拟存储体的配置。
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7.发明授权System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine 有权用于流水线硬件位图多位特里计算网络搜索引擎中的路径压缩优化的系统和方法公开(公告)号：US07715392B2
公开(公告)日：2010-05-11
申请号：US10317338
申请日：2002-12-12
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/54 , H04L45/7457
摘要： For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.
摘要翻译： 为了在路由器的流水线网络搜索引擎中使用，公开了用于消除单进入特技表的路径压缩优化系统和方法。 系统嵌入到父特技表（1）中包含数据包的公共前缀位的路径压缩模式，（2）跳过指示路径压缩模式长度的计数。 网络搜索引擎利用路径压缩模式和跳过计数来消除数据结构中的单条目特征表。 每个路径压缩模式在网络搜索引擎的后续流水线阶段中一次处理一步。 消除不必要的单进入trie表减少了内存空间，功耗以及遍历数据结构所需的内存访问次数。
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8.发明授权Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm 有权减少基于Trie的IP查找算法的流水线硬件实现中的查找延迟的机制公开(公告)号：US07924839B2
公开(公告)日：2011-04-12
申请号：US10313395
申请日：2002-12-06
IPC分类号： H04L12/28
CPC分类号： G06F17/30985
摘要： A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.
摘要翻译： 在多位特务的前缀搜索操作期间，每个处理步幅的一系列硬件流水线单元包括在除了最后一个流水线单元之外的至少一个流水线单元内，用于从相应流水线单元退出搜索结果的机制， 搜索结果通过剩余的管道单位。 提前退休可能是由于缺少要处理或完成的后续步骤（遗漏或结束节点匹配）的搜索，以及后续流水线单元中没有主动搜索操作可能触发。 早期退休机制可以被包括在对应于最后一步的流水线单元中，其最大前缀长度短于流水线（例如，20位或32位，而不是64位），以某种其他方式选择的流水线单元 管道单元。 前缀搜索操作的最差情况和/或平均延迟减少。
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公开(公告)号：US06694420B2
公开(公告)日：2004-02-17
申请号：US10008726
申请日：2001-12-05
申请人： Lun Bin Huang
发明人： Lun Bin Huang
IPC分类号： G06F1206
CPC分类号： G06F9/34 , G06F7/026 , G06F12/0875 , G06F12/0891
摘要： An address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2N address locations beginning at a base address location, B[M:0], is disclosed, wherein the address range checking circuit does not require a large comparator circuit. The address range checking circuit comprises: 1) comparison circuitry for determining if the address segment A[N−1:0] is less than the address segment B[N−1:0] and generating on a first control signal; 2) first equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] and generating an A=B status signal; 3) second equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] plus one and generating an A=B+1 status signal; and 4) a multiplexer that outputs the A=B status signal or the A=B+1 status signal depending on the value of the first control signal.
摘要翻译： 公开了一种地址范围检查电路，其能够确定目标地址A [M：0]是否在从基地址位置B [M：0]开始的具有2个N个地址位置的地址空间内，其中 地址范围检查电路不需要较大的比较器电路。 地址范围检查电路包括：1）用于确定地址段A [N-1：0]是否小于地址段B [N-1：0]并产生第一控制信号的比较电路; 2）用于确定地址段A [M：N]是否等于地址段B [M：N]并产生A = B状态信号的第一等价检测电路; 3）第二等效检测电路，用于确定地址段A [M：N]是否等于地址段B [M：N]加1，并产生A = B + 1状态信号; 以及4）多路复用器，其根据第一控制信号的值输出A = B状态信号或A = B + 1状态信号。
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10.发明授权Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes 有权通过压缩单长度前缀的表示来增加基于多比特特里硬件存储引擎中的存储容量的方法公开(公告)号：US07162481B2
公开(公告)日：2007-01-09
申请号：US10313854
申请日：2002-12-06
CPC分类号： G06F17/30985 , G06F17/30625 , Y10S707/959 , Y10S707/99933 , Y10S707/99934 , Y10S707/99942
摘要： Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.
摘要翻译： 在单个子表中每个包含相同长度前缀部分的端节点条目终止的前缀通过用子表中的一个或多个压缩单个长度（CSL）前缀条目替换结束节点条目而被压缩，该条目包含前缀部分的位图 结束节点条目。 为子表创建不同类型的父表格特里节点条目。 前缀部分为非零长度的位置，父表包含索引结束节点条目的位图。 在前缀部分的长度为零的情况下，父表可以可选地包含作为结束节点的前缀部分的位图。 在CSL节点条目中合并的前缀部分的数量基于前缀部分长度。
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