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公开(公告)号：US20160269665A1
公开(公告)日：2016-09-15
申请号：US15160575
申请日：2016-05-20
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
IPC: H04N5/374 , H04N9/04 , H04N5/3745 , H04N5/378
CPC classification number: H04N5/374 , H04N3/155 , H04N5/335 , H04N5/3741 , H04N5/37457 , H04N5/3765 , H04N5/378 , H04N9/045
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
Abstract translation: 固态成像装置能够简化像素结构以减小像素大小，并且能够抑制当提供多个输出系统时像素之间的特性的变化。 单位单元包括两个像素。 上下光电转换器和传输晶体管分别连接到上和下光电转换器，复位晶体管和放大晶体管形成两个像素。 全面信号线连接到复位晶体管和放大晶体管的各个漏极。 控制全面信号线以及传输信号线和复位信号线，以读出信号实现了像素中布线的简化，像素尺寸的缩小等。
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2.发明申请公开(公告)号：US20180122849A1
公开(公告)日：2018-05-03
申请号：US15858204
申请日：2017-12-29
Applicant: Sony Corporation
Inventor： Takashi Abe , Nobuo Nakamura , Keiji Mabuchi , Tomoyuki Umeda , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
IPC: H01L27/146 , H01L31/0232 , H01L31/0216 , H01L23/544
CPC classification number: H01L27/14643 , H01L23/544 , H01L27/14603 , H01L27/14607 , H01L27/14609 , H01L27/14612 , H01L27/1462 , H01L27/14623 , H01L27/14625 , H01L27/14627 , H01L27/1463 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14683 , H01L27/14685 , H01L27/14687 , H01L31/02162 , H01L31/0232 , H01L31/02327 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back-side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back-side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.
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公开(公告)号：US09859324B2
公开(公告)日：2018-01-02
申请号：US15225303
申请日：2016-08-01
Applicant: Sony Corporation
Inventor： Takashi Abe , Nobuo Nakamura , Keiji Mabuchi , Tomoyuki Umeda , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
IPC: H01L27/146 , H01L23/544 , H01L31/0216 , H01L31/0232
CPC classification number: H01L27/14643 , H01L23/544 , H01L27/14603 , H01L27/14607 , H01L27/14609 , H01L27/14612 , H01L27/1462 , H01L27/14623 , H01L27/14625 , H01L27/14627 , H01L27/1463 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14683 , H01L27/14685 , H01L27/14687 , H01L31/02162 , H01L31/0232 , H01L31/02327 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an acitve region may also be used for the registration mark. Thereafter, the registration mark is read from the back-side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back-side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.
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公开(公告)号：US09185369B2
公开(公告)日：2015-11-10
申请号：US13910859
申请日：2013-06-05
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
CPC classification number: H04N5/374 , H04N3/155 , H04N5/335 , H04N5/3741 , H04N5/37457 , H04N5/3765 , H04N5/378 , H04N9/045
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell (30) includes two pixels (31) and (32). Upper and lower photoelectric converters (33) and (34), transfer transistors (35) and (36) connected to the upper and lower photoelectric converters, respectively, a reset transistor (37), and an amplifying transistor (38) form the two pixels (31) and (32). A full-face signal line 39 is connected to the respective drains of the reset transistor (37) and the amplifying transistor (38). Controlling the full-face signal line (39), along with transfer signal lines (42) and (43) and a reset signal line (41), to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
Abstract translation: 固态成像装置能够简化像素结构以减小像素大小，并且能够抑制当提供多个输出系统时像素之间的特性的变化。 单位单元（30）包括两个像素（31）和（32）。 上，下光电转换器（33）和（34）分别连接到上，下光电转换器的转移晶体管（35）和（36），复位晶体管（37）和放大晶体管（38） 像素（31）和（32）。 全面信号线39连接到复位晶体管（37）和放大晶体管（38）的各个漏极。 控制全面信号线（39）以及传输信号线（42）和（43）和复位信号线（41），以读出信号实现了像素中布线的简化，减少了 像素大小等等。
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公开(公告)号：US20190342512A1
公开(公告)日：2019-11-07
申请号：US16511876
申请日：2019-07-15
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
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Patent Agency Ranking
公开(公告)号：US10263033B2
公开(公告)日：2019-04-16
申请号：US15858204
申请日：2017-12-29
Applicant: Sony Corporation
Inventor： Takashi Abe , Nobuo Nakamura , Keiji Mabuchi , Tomoyuki Umeda , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
IPC: H01L27/146 , H01L23/544 , H01L31/0216 , H01L31/0232
Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back-side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back-side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.
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公开(公告)号：US09832405B2
公开(公告)日：2017-11-28
申请号：US15160575
申请日：2016-05-20
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
CPC classification number: H04N5/374 , H04N3/155 , H04N5/335 , H04N5/3741 , H04N5/37457 , H04N5/3765 , H04N5/378 , H04N9/045
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
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公开(公告)号：US20160014304A1
公开(公告)日：2016-01-14
申请号：US14864169
申请日：2015-09-24
Applicant: Sony Corporation
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
CPC classification number: H04N5/374 , H04N3/155 , H04N5/335 , H04N5/3741 , H04N5/37457 , H04N5/3765 , H04N5/378 , H04N9/045
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell (30) includes two pixels (31) and (32). Upper and lower photoelectric converters (33) and (34), transfer transistors (35) and (36) connected to the upper and lower photoelectric converters, respectively, a reset transistor (37), and an amplifying transistor (38) form the two pixels (31) and (32). A full-face signal line 39 is connected to the respective drains of the reset transistor (37) and the amplifying transistor (38). Controlling the full-face signal line (39), along with transfer signal lines (42) and (43) and a reset signal line (41), to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
Abstract translation: 固态成像装置能够简化像素结构以减小像素大小，并且能够抑制当提供多个输出系统时像素之间的特性的变化。 单位单元（30）包括两个像素（31）和（32）。 上，下光电转换器（33）和（34）分别连接到上，下光电转换器的转移晶体管（35）和（36），复位晶体管（37）和放大晶体管（38） 像素（31）和（32）。 全面信号线39连接到复位晶体管（37）和放大晶体管（38）的各个漏极。 控制全面信号线（39）以及传输信号线（42）和（43）和复位信号线（41），以读出信号实现了像素中布线的简化，减少了 像素大小等。
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公开(公告)号：US10778918B2
公开(公告)日：2020-09-15
申请号：US16511876
申请日：2019-07-15
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
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公开(公告)号：US20190174083A1
公开(公告)日：2019-06-06
申请号：US16201692
申请日：2018-11-27
Applicant: SONY CORPORATION
Inventor： Takashi Abe , Nobuo Nakamura , Tomoyuki Umeda , Keiji Mabuchi , Hiroaki Fujita , Eiichi Funatsu , Hiroki Sato
Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.
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