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    COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE
    1.
    发明申请
    COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE 审中-公开
    大容量存储设备中的命令完成检测

    公开(公告)号：US20090172213A1

    公开(公告)日：2009-07-02

    申请号：US11968042

    申请日：2007-12-31

    申请人： Sowmiya Jayachandran ,  Jawad B. Khan ,  Randall K. Webb ,  Robert W. Faber

    发明人： Sowmiya Jayachandran ,  Jawad B. Khan ,  Randall K. Webb ,  Robert W. Faber

    IPC分类号： G06F3/00

    CPC分类号： G06F3/0659 ,  G06F3/0625 ,  G06F3/0679 ,  Y02D10/154

    摘要： In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，在发出存储器命令之后的停止时间过去之后，执行状态读取操作以确定存储器命令的状态。 在一些实施例中，如果存储器命令尚未完成，则轮询间隔被用于执行状态读取操作以在轮询间隔期满之后确定存储器命令的状态，并重复该过程直到存储器命令已经完成 。 描述和要求保护其他实施例。

    Adjustable programming speed for NAND memory devices
    2.
    发明授权
    Adjustable programming speed for NAND memory devices 有权
    NAND存储器件可编程速度可调

    公开(公告)号：US08595597B2

    公开(公告)日：2013-11-26

    申请号：US13039553

    申请日：2011-03-03

    申请人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

    发明人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

    IPC分类号： G11C29/00 ,  G06F11/00

    CPC分类号： G06F11/1048 ,  G11C16/00 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

    摘要翻译： 本发明的实施例描述了通过有效利用为设备执行的纠错码来改善固态设备（SSD）写入速度的方法，系统和装置。 SSD可以由多个NAND存储器件组成。 应当理解，这样的设备倾向于具有与设备的编程/擦除周期计数相关的原始误码率（RBER）。 本发明的实施例通过改变SSD的操作条件来有效地使用系统ECC，以更好地利用所实施的ECC算法的鲁棒性。 例如，本发明的实施例可以改变提供给SSD的编程电压以增加写入速度; 这样的增加可能增加设备的RBER，但是由于为终端存储保真度（即，将在生命结束时发生的RBER）提供的ECC而不会影响这种操作的准确性。

    ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES
    3.
    发明申请
    ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES 有权
    用于NAND存储器件的可调节编程速度

    公开(公告)号：US20120226959A1

    公开(公告)日：2012-09-06

    申请号：US13039553

    申请日：2011-03-03

    申请人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

    发明人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G11C16/00 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

    摘要翻译： 本发明的实施例描述了通过有效利用为设备执行的纠错码来改善固态设备（SSD）写入速度的方法，系统和装置。 SSD可以由多个NAND存储器件组成。 应当理解，这样的设备倾向于具有与设备的编程/擦除周期计数相关的原始误码率（RBER）。 本发明的实施例通过改变SSD的操作条件来有效地使用系统ECC，以更好地利用所实施的ECC算法的鲁棒性。 例如，本发明的实施例可以改变提供给SSD的编程电压以增加写入速度; 这样的增加可能增加设备的RBER，但是由于为终端存储保真度（即，将在生命结束时发生的RBER）提供的ECC而不会影响这种操作的准确性。

    Recovering from a non-volatile memory failure
    4.
    发明授权
    Recovering from a non-volatile memory failure 有权
    从非易失性存储器故障中恢复

    公开(公告)号：US07516267B2

    公开(公告)日：2009-04-07

    申请号：US11266119

    申请日：2005-11-03

    申请人： Richard L. Coulson ,  Sanjeev N. Trika ,  Robert W. Faber

    发明人： Richard L. Coulson ,  Sanjeev N. Trika ,  Robert W. Faber

    IPC分类号： G06F12/16

    CPC分类号： G11C16/349 ,  G06F12/0246

    摘要： Write operations store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. Sequence information stored in the physical memory location indicates which one of the write operations occurred last. The available erased memory location can be split into a list of erased memory locations available to be used and a list of erased memory locations not available to be used. Then, on a failure, only the list of erased memory locations available to be used needs to be analyzed to reconstruct the consumption states of memory locations.

    摘要翻译： 写操作将数据存储在不同的物理内存位置。 每个物理存储器位置与物理地址中共同共享的逻辑地址相关联。 存储在物理存储器位置的序列信息指示最后发生哪个写入操作。 可用的擦除的存储器位置可以被拆分为可用于被使用的擦除的存储器位置的列表和不可用的擦除的存储器位置的列表。 然后，在故障时，仅需要分析可用于被使用的擦除的存储器位置的列表，以重建存储器位置的消耗状态。

    Nonvolatile memory wear management
    7.
    发明授权
    Nonvolatile memory wear management 有权
    非易失性内存磨损管理

    公开(公告)号：US09141536B2

    公开(公告)日：2015-09-22

    申请号：US13991392

    申请日：2011-11-04

    申请人： Robert W. Faber

    发明人： Robert W. Faber

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C16/34

    CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/349

    摘要： Embodiments describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. Specifically, embodiments may include a memory controller to receive a memory access request directed to a storage unit of the nonvolatile memory. The memory controller may access metadata in the storage unit and determine whether to perform a memory access in accordance with the memory access request based on the state information. Other embodiments may be described or claimed.

    摘要翻译： 实施例描述了用于在非易失性存储器中提供目标磨损管理的方法，装置和系统配置。 具体地，实施例可以包括存储器控制器，用于接收针对非易失性存储器的存储单元的存储器访问请求。 存储器控制器可以访问存储单元中的元数据，并且基于状态信息来确定是否根据存储器访问请求执行存储器访问。 可以描述或要求保护其他实施例。

    FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY
    9.
    发明申请
    FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY 有权
    非易失性存储器的灵活磨损管理

    公开(公告)号：US20140143474A1

    公开(公告)日：2014-05-22

    申请号：US13682885

    申请日：2012-11-21

    申请人： Prashant S. Damle ,  Robert W. Faber ,  Ningde Xie

    发明人： Prashant S. Damle ,  Robert W. Faber ,  Ningde Xie

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7211

    摘要： Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

    摘要翻译： 可以实现跨存储器单元地址空间的写周期更均匀分布的存储器单元磨损管理的系统和方法。 这些系统和方法允许经受大量写入周期的存储器单元的物理地址与经受较少写入周期的存储器单元的物理地址交换。 如果该存储单元组的写周期计数超过指定的阈值，则一组存储单元的物理地址是“热地址”。 如果一组存储单元的写周期计数不超过指定的阈值，则该存储单元组的物理地址为“冷地址”。 系统和方法允许指定的写周期计数阈值动态增加，以确保冷地址可用于与存储单元地址空间中的热地址进行交换。