公开(公告)号：US09251060B2

公开(公告)日：2016-02-02

申请号：US13996173

申请日：2012-03-29

申请人： Jawad B. Khan ,  Richard L. Coulson

发明人： Jawad B. Khan ,  Richard L. Coulson

IPC分类号： G06F12/02 ,  G11C16/10 ,  G11C11/56 ,  G06F11/10

CPC分类号： G06F12/0246 ,  G06F11/1012 ,  G06F12/0253 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641

摘要： Described herein are embodiments of an apparatus configured for compression-enabled blending of data, a system including the apparatus configured for compression-enabled blending of data, and a method for compression-enabled blending of data. An apparatus configured for compression-enabled blending of data may include non-volatile memory configured to operate in a single-level cell mode and a multi-level cell mode, a compression module configured to compress data to generate compressed data, and a memory controller configured to write, in response to a reduction ratio of the compressed data being less than a threshold compression ratio, a first portion of the compressed data to the non-volatile memory in the single-level cell mode, and a second portion of the compressed data to the non-volatile memory in the multi-level cell mode. Other embodiments may be described and/or claimed.

摘要翻译： 这里描述了被配置用于数据的压缩启用混合的装置的实施例，包括被配置为用于数据的压缩启用的混合的装置的系统以及用于数据压缩的混合的方法。 被配置为用于数据压缩启用的混合的装置可以包括被配置为以单级单元模式和多级单元模式操作的非易失性存储器，被配置为压缩数据以产生压缩数据的压缩模块以及存储器控制器 被配置为响应于小于阈值压缩比的压缩数据的缩小比率将压缩数据的第一部分写入单级单元模式中的非易失性存储器，并且压缩的第二部分 数据到多级单元模式下的非易失性存储器。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150149695A1

公开(公告)日：2015-05-28

申请号：US14091598

申请日：2013-11-27

申请人： Jawad B. Khan ,  Knut S. Grimsrud ,  Richard L. Coulson

发明人： Jawad B. Khan ,  Knut S. Grimsrud ,  Richard L. Coulson

IPC分类号： G06F3/06

CPC分类号： G06F3/0641 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0688 ,  G06F17/30109 ,  G06F2003/0697 ,  G06F2212/402

摘要： A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.

摘要翻译： 重复数据删除方法利用SSD中的加速硬件来执行重复数据删除操作中使用的摘要计算，代表附件主机进行支持，从而减轻了重复数据删除中的摘要计算的计算负担（de-dupe ）处理。 去重处理通常涉及消息摘要（MD）和/或散列函数的计算和比较。 这样的MD功能通常也用于加密操作，例如加密和认证。 通常，SSD包括用于与SSD的安全功能相关联的MD功能的板载硬件加速器。 然而，也可以调用硬件加速器来计算消息摘要结果并将结果返回到主机，类似于外部硬件加速器，从主机有效地卸载MD计算的负担，但是不需要重定向数据，因为摘要计算 在通过SSD进行存储的数据流上执行。

公开(公告)号：US20140250257A1

公开(公告)日：2014-09-04

申请号：US13996173

申请日：2012-03-29

申请人： Jawad B. Khan ,  Richard L. Coulson

发明人： Jawad B. Khan ,  Richard L. Coulson

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F11/1012 ,  G06F12/0253 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641

摘要： Described herein are embodiments of an apparatus configured for compression-enabled blending of data, a system including the apparatus configured for compression-enabled blending of data, and a method for compression-enabled blending of data. An apparatus configured for compression-enabled blending of data may include non-volatile memory configured to operate in a single-level cell mode and a multi-level cell mode, a compression module configured to compress data to generate compressed data, and a memory controller configured to write, in response to a reduction ratio of the compressed data being less than a threshold compression ratio, a first portion of the compressed data to the non-volatile memory in the single-level cell mode, and a second portion of the compressed data to the non-volatile memory in the multi-level cell mode. Other embodiments may be described and/or claimed.

摘要翻译： 这里描述了被配置用于数据的压缩启用混合的装置的实施例，包括被配置为用于数据的压缩启用的混合的装置的系统以及用于数据压缩的混合的方法。 被配置为用于数据压缩启用的混合的装置可以包括被配置为以单级单元模式和多级单元模式操作的非易失性存储器，被配置为压缩数据以产生压缩数据的压缩模块以及存储器控制器 被配置为响应于小于阈值压缩比的压缩数据的缩小比率将压缩数据的第一部分写入单级单元模式中的非易失性存储器，并且压缩的第二部分 数据到多级单元模式下的非易失性存储器。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130007346A1

公开(公告)日：2013-01-03

申请号：US13175534

申请日：2011-07-01

申请人： Jawad B. Khan

发明人： Jawad B. Khan

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3071 ,  H03M7/55 ,  H03M7/6082 ,  Y02D10/13

摘要： Described are embodiments of methods, apparatus, and systems for detecting incompressible data and selectively compressing compressible data without compressing the incompressible data. A method may include determining a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, determining that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold, and compressing the second data of the plurality of input data. Other embodiments may be described and claimed.

摘要翻译： 描述了用于检测不可压缩数据的方法，装置和系统的实施例，并且在不压缩不可压缩数据的情况下选择性地压缩可压缩数据。 方法可以包括确定多个输入数据中的第一数据的第一可压缩值和多个输入数据的第二数据的第二可压缩值，至少部分地基于第一可压缩性值确定第一数据是不可压缩的 并压缩多个输入数据的第二数据。 可以描述和要求保护其他实施例。

公开(公告)号：US20170091022A1

公开(公告)日：2017-03-30

申请号：US14866291

申请日：2015-09-25

申请人： JAWAD B. KHAN ,  ANAND S. RAMALINGAM ,  PRANAV KALAVADE

发明人： JAWAD B. KHAN ,  ANAND S. RAMALINGAM ,  PRANAV KALAVADE

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/108 ,  G11C29/52 ,  G11C2029/0411

摘要： Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.

公开(公告)号：US20150355704A1

公开(公告)日：2015-12-10

申请号：US14827497

申请日：2015-08-17

申请人： Knut S. Grimsrud ,  Jawad B. Khan

发明人： Knut S. Grimsrud ,  Jawad B. Khan

IPC分类号： G06F1/32 ,  G06F3/06

CPC分类号： G06F1/3268 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D50/20

摘要： Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD, while maintaining low resume latency upon exiting a reduced power state. By arranging a storage controller and at least one NAND flash package of the SSD in separate power islands, storing context information for the SSD in at least one page buffer of NAND flash memory within the NAND flash package on one power island upon entering the reduced power state, and, once the context information is stored in the page buffer, allowing the NAND flash memory to enter a standby mode, placing the storage controller on the other power island in a predefined low power mode, and removing power from any unneeded components on the same power island as the storage controller, a scalable approach to reducing idle power levels in the SSD can be achieved.

摘要翻译： 降低诸如固态硬盘（SSD）的固态存储设备中的能量消耗的装置和方法，其可以降低SSD中的空闲功率水平，同时在降低功率状态时保持低的恢复等待时间。 通过在独立的功率岛中布置存储控制器和SSD的至少一个NAND闪存封装，在输入降低的功率时，在一个功率岛上的NAND闪存封装内的NAND闪存的至少一个页缓冲器中存储SSD的上下文信息 状态，并且一旦将上下文信息存储在页面缓冲器中，允许NAND闪存进入待机模式，将存储控制器以预定义的低功率模式放置在另一个功率岛上，并且从任何不需要的组件上去除功率 与存储控制器相同的功率岛，可以实现降低SSD中空闲功率水平的可扩展方法。

公开(公告)号：US20120226959A1

公开(公告)日：2012-09-06

申请号：US13039553

申请日：2011-03-03

申请人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

发明人： Ningde Xie ,  Matthew Goldman ,  Jawad B. Khan ,  Robert W. Faber

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G11C16/00 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

摘要： Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

摘要翻译： 本发明的实施例描述了通过有效利用为设备执行的纠错码来改善固态设备（SSD）写入速度的方法，系统和装置。 SSD可以由多个NAND存储器件组成。 应当理解，这样的设备倾向于具有与设备的编程/擦除周期计数相关的原始误码率（RBER）。 本发明的实施例通过改变SSD的操作条件来有效地使用系统ECC，以更好地利用所实施的ECC算法的鲁棒性。 例如，本发明的实施例可以改变提供给SSD的编程电压以增加写入速度; 这样的增加可能增加设备的RBER，但是由于为终端存储保真度（即，将在生命结束时发生的RBER）提供的ECC而不会影响这种操作的准确性。

公开(公告)号：US08001444B2

公开(公告)日：2011-08-16

申请号：US11835878

申请日：2007-08-08

申请人： Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

发明人： Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

IPC分类号： G11C29/00

CPC分类号： G11B20/18 ,  G06F11/108 ,  G11B20/10527 ,  G11B2020/1062

摘要： A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

摘要翻译： 多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。 缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。 主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。 这种纠错引擎可以防止缓冲存储器和存储信道中的数据错误。

公开(公告)号：US20160259568A1

公开(公告)日：2016-09-08

申请号：US15025935

申请日：2013-11-26

申请人： Knut S. GRIMSRUD ,  Jawad B. KHAN

发明人： Knut S. GRIMSRUD ,  Jawad B. KHAN

IPC分类号： G06F3/06 ,  G06F13/42

CPC分类号： G06F3/0613 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0683 ,  G06F3/0685 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0026

摘要： An SSD controller operates as an interface device conversant in a host protocol and a storage protocol supporting respective host and storage interfaces for providing a host with a view of an entire storage system. The host has visibility of the storage protocol that presents the storage system as a logical device, and accesses the storage device through the host protocol which is adapted for accessing high speed devices such as solid state drives (SSDs). The storage protocol supports a variety of possible dissimilar devices, allowing the host effective access to a combination of SSD and traditional storage as defined by the storage system. In this manner, a host protocol such as NVMe (Non-Volatile Memory Express), well suited to SSDs, permits efficient access to storage systems, such as a storage array, thus the entire storage system (array or network) is presented to an upstream host as an NVMe storage device.

摘要翻译： SSD控制器作为在主机协议和存储协议中熟悉的接口设备操作，支持相应的主机和存储接口，以向主机提供整个存储系统的视图。 主机可以看到将存储系统呈现为逻辑设备的存储协议，并通过适用于访问高速设备（如固态硬盘（SSD））的主机协议访问存储设备。 存储协议支持各种可能的不同设备，允许主机有效地访问由存储系统定义的SSD和传统存储的组合。 以这种方式，非常适合于SSD的诸如NVMe（非易失性存储器Express）的主机协议允许对诸如存储阵列的存储系统的有效访问，从而将整个存储系统（阵列或网络）呈现给 上游主机作为NVMe存储设备。

公开(公告)号：US20150154066A1

公开(公告)日：2015-06-04

申请号：US14093936

申请日：2013-12-02

申请人： Knut S. Grimsrud ,  Jawad B. Khan

发明人： Knut S. Grimsrud ,  Jawad B. Khan

IPC分类号： G06F11/10

CPC分类号： G06F11/108 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1064 ,  G06F11/1068 ,  G06F11/1076 ,  G06F2211/1009 ,  G06F2211/109

摘要： A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

摘要翻译： 固态硬盘（SSD）纠错机制的寻呼方案，用于交换存储页面上下文的其余部分的SRAM和较不昂贵的DRAM之间的诸如页面之间的奇偶校验分量的部分。 奇偶校验操作将XOR函数应用于上下文页面中的相应存储器位置。 专用纠错（奇偶校验）SRAM只需要足够的存储器来存储奇偶校验操作（XOR）所在的存储器部分，通常是页面的高速缓存行。 上下文中的剩余部分被高速缓存逻辑交换或分页，使得整个上下文被奇偶校验操作迭代地处理（异或）。