公开(公告)号：US08504756B2

公开(公告)日：2013-08-06

申请号：US13118493

申请日：2011-05-30

申请人： Srinivasa Rao Kothamasu ,  Sreenath Shambu Ramakrishna

发明人： Srinivasa Rao Kothamasu ,  Sreenath Shambu Ramakrishna

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/4031 ,  G06F2213/0038

摘要： A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request.

摘要翻译： 公开了一种用于使用桥接电路来提高用于高延迟外设读取访问的片上系统（SoC）带宽性能的系统，电路和方法。 在一个实施例中，SoC包括桥接电路，一个或多个总线主器件，至少一个高带宽总线从器件和至少一个低带宽总线从器件，其通过高带宽总线和低带宽总线通信耦合。 此外，总线主机通过预先向安排的读取事务请求发出早期读取事务请求来访问至少一个低带宽总线从机。 此外，桥接电路接收早期读取事务请求并且获取与早期读取事务请求相关联的数据。 此外，桥接电路接收预定的读取事务请求。 然后，在接收到预定的读取事务请求后，将获取的数据发送到总线主机。

公开(公告)号：US20140025852A1

公开(公告)日：2014-01-23

申请号：US13553255

申请日：2012-07-19

申请人： Sreenath Shambu Ramakrishna ,  Srinivasa Rao Kothamasu ,  Debjit Roy Choudhury

发明人： Sreenath Shambu Ramakrishna ,  Srinivasa Rao Kothamasu ,  Debjit Roy Choudhury

IPC分类号： G06F13/14

CPC分类号： G06F13/14 ,  G06F12/0284 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

摘要： A bus interconnect for interconnecting one or more master devices with one or more slave devices in a system includes at least one slave interface module adapted for communicating with a corresponding one of the master devices and at least one master interface module adapted for communicating with a corresponding one of the slave devices. The bus interconnect further includes a configurable response module coupled with the slave interface module. The configurable response module is operative to generate different configurable responses associated with access requests to corresponding portions of an address space of the system.

摘要翻译： 用于将一个或多个主设备与系统中的一个或多个从设备互连的总线互连包括至少一个从接口模块，其适于与相应的一个主设备通信，以及至少一个主接口模块，适于与对应的通信 其中一个从设备。 总线互连还包括与从接口模块耦合的可配置响应模块。 可配置响应模块可操作以产生与对系统的地址空间的对应部分的访问请求相关联的不同可配置响应。

公开(公告)号：US20130111181A1

公开(公告)日：2013-05-02

申请号：US13286109

申请日：2011-10-31

申请人： Srinivasa Rao Kothamasu ,  George Wayne Nation ,  Krishna Venkanna Bhandi

发明人： Srinivasa Rao Kothamasu ,  George Wayne Nation ,  Krishna Venkanna Bhandi

IPC分类号： G06F12/08

CPC分类号： G06F12/0284 ,  G06F12/06 ,  G06F12/0888 ,  G06F2212/1008 ,  G06F2212/206

摘要： A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when addressing the device within the first mapped address region and to access the device in accordance with a second set of memory attributes when addressing the device within the second mapped address region. The first set of memory attributes is different from the second set of memory attributes.

摘要翻译： 数据处理系统包括设备和设备访问电路。 该设备被映射到第一映射地址区域和第二映射地址区域。 在寻址第一映射地址区域内的设备时，设备访问电路又可操作以根据第一组存储器属性访问设备，并且当寻址存储器属性时，根据第二组存储器属性访问设备 设备在第二映射地址区域内。 第一组内存属性与第二组内存属性不同。

公开(公告)号：US08924779B2

公开(公告)日：2014-12-30

申请号：US13435613

申请日：2012-03-30

申请人： George Wayne Nation ,  Gary M. Lippert ,  Srinivasa Rao Kothamasu

发明人： George Wayne Nation ,  Gary M. Lippert ,  Srinivasa Rao Kothamasu

IPC分类号： G06F11/00

CPC分类号： G06F11/0757 ,  G06F11/079 ,  G06F11/1428

摘要： An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation.

摘要翻译： 提供一种用于处理硬件系统中的异常的装置，包括主设备和通过互连设备与主设备耦合的至少一个从设备。 该装置包括至少一个控制器，用于接收与从属设备相关的状态信息。 状态信息表示从属设备和/或互连设备中是否存在异常。 控制器可操作以根据与从属设备有关的状态信息的函数产生输出响应信息，用于以减少硬件系统复位以恢复正常操作的方式检测和/或响应硬件系统异常。

公开(公告)号：US20130166938A1

公开(公告)日：2013-06-27

申请号：US13334885

申请日：2011-12-22

申请人： Sathappan Palaniappan ,  Srinivasa Rao Kothamasu ,  Deepak Ashok Naik

发明人： Sathappan Palaniappan ,  Srinivasa Rao Kothamasu ,  Deepak Ashok Naik

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.

摘要翻译： 数据处理系统包括根据第一时钟信号操作的处理器和根据第二时钟信号操作的存储器。 数据处理系统使得处理器至少部分地响应于来自第一同步电路的信号和来自第二同步电路的信号从存储器读取数据。 第一同步电路包括第一存储元件，其对与第二时钟信号同步的信号与对第一存储元件的输出进行采样的第二存储元件组合进行采样。 第一和第二存储元件由第一时钟信号中的反向转换触发。 第二同步电路包括以类似方式配置的第三和第四存储元件，除了它们对与第一时钟信号同步的信号进行采样，并且由第二时钟信号中的反向转换触发。

公开(公告)号：US08667196B2

公开(公告)日：2014-03-04

申请号：US13455744

申请日：2012-04-25

申请人： Srinivasa Rao Kothamasu ,  Debjit Roy Choudhury ,  Dharmesh Kishor Tirthdasani ,  Sajith Kizhakke Kalathil Achuthan Kutty ,  Jean Jacob

发明人： Srinivasa Rao Kothamasu ,  Debjit Roy Choudhury ,  Dharmesh Kishor Tirthdasani ,  Sajith Kizhakke Kalathil Achuthan Kutty ,  Jean Jacob

IPC分类号： G06F13/00

CPC分类号： G06F13/404

摘要： A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

摘要翻译： 提供了一种用于映射一个或多个从设备之间的地址和多层互连系统中的至少一个对应的主设备的方法和设备，该多层互连系统包括用于在一个或多个从设备与主设备之间进行接口的多个总线矩阵。 所述方法和装置可操作用于接收对应于系统的地址映射，通过至少一个总线矩阵接收关于一个或多个从属设备的连通性的信息，确定主设备是否具有多于一个与之相关的默认从单元， 并且当所述主设备具有多于一个与之相关联的默认从单元时，产生第一和第二地址映射，并且将所述系统配置为每个主设备具有不超过一个默认从单元。

公开(公告)号：US20130314819A1

公开(公告)日：2013-11-28

申请号：US13481900

申请日：2012-05-28

申请人： Debjit Roy Choudhury ,  Srinivasa Rao Kothamasu ,  Karthik Satyanarayan Murthy Akella

发明人： Debjit Roy Choudhury ,  Srinivasa Rao Kothamasu ,  Karthik Satyanarayan Murthy Akella

IPC分类号： G11B5/004 ,  G11B5/127

CPC分类号： G11B5/004 ,  G11B5/54 ,  G11B5/58 ,  Y10T29/49021

摘要： An electronic storage system includes a first cylindrical storage area. The first cylindrical storage area is configured to rotate about an axis. The first cylindrical storage area includes a first storage surface. The storage system further includes a first access head, configured to access information stored on the first storage surface, and a first head arm. The first access head is disposed on the first head arm. A corresponding method, cylindrical storage area, and head access assembly are also provided.

摘要翻译： 电子存储系统包括第一圆柱形存储区域。 第一圆柱形存储区域被配置为围绕轴线旋转。 第一圆柱形存储区域包括第一存储表面。 存储系统还包括：第一接入头，被配置为访问存储在第一存储表面上的信息和第一头臂。 第一进入头设置在第一头臂上。 还提供了相应的方法，圆柱形存储区域和头部存取组件。

公开(公告)号：US08923087B2

公开(公告)日：2014-12-30

申请号：US13354222

申请日：2012-01-19

申请人： Romeshkumar Bharatkumar Mehta ,  Dharmesh Kishor Tirthdasani ,  Srinivasa Rao Kothamasu ,  Ravindra Bidnur

发明人： Romeshkumar Bharatkumar Mehta ,  Dharmesh Kishor Tirthdasani ,  Srinivasa Rao Kothamasu ,  Ravindra Bidnur

IPC分类号： G06F1/30 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3275 ,  G11C5/148 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

摘要： A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

摘要翻译： 提供了一种控制存储器件的功率模式的方法，其包括响应于控制信号和频率信息提供功率模式控制信号。 控制信号由可操作地耦合到存储器件的处理设备提供。 频率信息与用于操作处理装置的时钟信号相关联，并且功率模式控制信号用于控制功率模式。 控制信号包括芯片选择（CS）信号和/或等待中断（WFI）信号，并且功率模式包括轻睡眠（LS）模式和/或深度睡眠（DS）模式。 频率信息表示低频范围，中频范围和/或高频范围。 还公开了相应的计算机可读介质，功率管理控制器和电子系统。

公开(公告)号：US08583844B2

公开(公告)日：2013-11-12

申请号：US13118603

申请日：2011-05-31

申请人： Sakthivel Komarasamy Pullagoundapatti ,  Srinivasa Rao Kothamasu ,  Venkat Rao Vallapaneni ,  Claus Pribbernow ,  Shrinivas Sureban

发明人： Sakthivel Komarasamy Pullagoundapatti ,  Srinivasa Rao Kothamasu ,  Venkat Rao Vallapaneni ,  Claus Pribbernow ,  Shrinivas Sureban

IPC分类号： G06F13/00 ,  G06F13/364

CPC分类号： G06F13/364 ,  G06F13/4022 ,  G06F15/17312 ,  G06F2213/0038

摘要： A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

摘要翻译： 公开了一种基于多层互连片上系统（SOC）架构中的多个主机与多个从机之间的稀疏连接来优化从事事务ID宽度的系统和方法。 在一个实施例中，为第一处理子系统和包括多个主器件和多个从器件的第二处理子系统计算从事事务ID宽度。 此外，基于所计算的从事事务ID宽度，生成针对第一处理子系统和第二处理子系统中的任何从属设备的每个主机的从事事务ID。 此外，多个主站和多个从站之间的稀疏连接信息通过第一处理子系统中的第一总线矩阵来确定。 然后，通过根据稀疏连接信息去除每个生成的从事事务ID中的无关位，来生成第一处理子系统中的每个主设备到每个主设备的第一优化的从事事务ID。

公开(公告)号：US08533377B2

公开(公告)日：2013-09-10

申请号：US13118376

申请日：2011-05-28

申请人： Venkat Rao Vallapaneni ,  Srinivasa Rao Kothamasu ,  Sakthivel Komarasamy Pullagoundapatti

发明人： Venkat Rao Vallapaneni ,  Srinivasa Rao Kothamasu ,  Sakthivel Komarasamy Pullagoundapatti

IPC分类号： G06F13/00 ,  G06F13/364

CPC分类号： G06F13/364

摘要： A system and method for allocating transaction ID in a system with a plurality of processing modules is disclosed. In one embodiment, a method for assigning transaction ID to a processing module in a network on a chip system (NOCS) with a plurality of processing modules is disclosed. An address space is provided to each of the processing modules. A portion of the address space is selected. A subset of the selected portion of the address space for each of the processing module is selected as Valid Bits. The Valid Bits of the processing module is associated to a transaction ID.

摘要翻译： 公开了一种用于在具有多个处理模块的系统中分配事务ID的系统和方法。 在一个实施例中，公开了一种用于将事务ID分配给具有多个处理模块的芯片系统（NOCS）上的网络中的处理模块的方法。 向每个处理模块提供地址空间。 选择一部分地址空间。 选择每个处理模块的地址空间的所选部分的子集作为有效位。 处理模块的有效位与事务ID相关联。