公开(公告)号：US20120072784A1

公开(公告)日：2012-03-22

申请号：US12884305

申请日：2010-09-17

申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC分类号： G06F11/00

CPC分类号： G06F11/267

摘要： An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

摘要翻译： 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

公开(公告)号：US08335249B1

公开(公告)日：2012-12-18

申请号：US12626379

申请日：2009-11-25

申请人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/0272 ,  H04L25/061

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

摘要翻译： 集成电路（IC）上的均衡器电路包括串联连接的第一，第二和第三连续时间的均衡器级。 每个阶段包括峰值电感电路。 均衡器电路可以进一步包括可控制的，静态的，直流模式偏移电压补偿电路和/或动态连续模式偏移电压补偿电路，用于分别减小DC电压偏移和/或时变，连续模式电压偏移 应用该输出的第三均衡器级和利用电路。 第一均衡器级可以在具有可控制可变阻抗的终端电路之前。 差分电路和信令可用于各种电路组件。 均衡器电路对于使用28nm CMOS技术的可编程IC的一部分进行制造以及作为具有20-25Gbps的比特率的高速串行数据信号的接收机均衡器是特别有用的。

公开(公告)号：US08228102B1

公开(公告)日：2012-07-24

申请号：US12717062

申请日：2010-03-03

申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条 侧。 可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。 另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。 每个PMA三元组模块包括第一，第二和第三通道。 第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。 还公开了其它实施例和特征。

公开(公告)号：US08183921B1

公开(公告)日：2012-05-22

申请号：US12954090

申请日：2010-11-24

申请人： Sriram Narayan ,  Xiaoyan Su ,  Sergey Shumarayev

发明人： Sriram Narayan ,  Xiaoyan Su ,  Sergey Shumarayev

IPC分类号： H03F3/45

CPC分类号： H03F1/30 ,  H03F3/45197 ,  H03F3/45973 ,  H03F2200/375 ,  H03F2200/405 ,  H03F2203/45354 ,  H03F2203/45374

摘要： One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及配置有偏移消除环路的连续时间电路。 连续时间电路包括多级放大器链，包括第一放大级和最后的放大级，以及偏移消除环。 偏移消除环路被配置为接收最后的放大器级的输出并且向第一放大器级提供偏移校正电压信号。 偏移补偿环路可以产生一个主极点和单个后续寄生极点，以便具有更大的稳定性，并且可以有利地在较高频率处实现响应幅度的二阶滚降。 还公开了其它实施例，方面和特征。

公开(公告)号：US09444656B2

公开(公告)日：2016-09-13

申请号：US13289791

申请日：2011-11-04

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Sriram Narayan

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Sriram Narayan

IPC分类号： H04L25/03

CPC分类号： H04L25/03038 ,  H04L25/03146 ,  H04L2025/03573

摘要： One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种用于数据链路的接收机电路。 接收机电路至少包括第一信号路径，第二信号路径和路径选择器电路。 第一信号路径包括第一均衡电路，第二信号路径包括第二均衡电路。 路径选择器电路被配置为选择第一和第二信号路径的一个信号路径。 还公开了其它实施例和特征。

公开(公告)号：US08537886B1

公开(公告)日：2013-09-17

申请号：US13541917

申请日：2012-07-05

申请人： Xiaoyan Su ,  Sriram Narayan ,  Sergey Shumarayev

发明人： Xiaoyan Su ,  Sriram Narayan ,  Sergey Shumarayev

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L25/03038

摘要： Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

公开(公告)号：US08188792B1

公开(公告)日：2012-05-29

申请号：US12889772

申请日：2010-09-24

申请人： Sriram Narayan ,  Sergey Shumarayev

发明人： Sriram Narayan ,  Sergey Shumarayev

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  G05F3/262 ,  H03F2203/45244

摘要： A circuit includes a current mirror circuit and first and second transistors coupled as a differential pair. A first input voltage is provided to a control input of the first transistor. A second input voltage is provided to a control input of the second transistor. The current mirror circuit includes a third transistor, a fourth transistor coupled to the third transistor, and a fifth transistor coupled in series with the fourth transistor. The third transistor provides a current through the differential pair that is proportional to a current through the fourth transistor. A control input of the fourth transistor is coupled between the fifth transistor and a source of current.

摘要翻译： 电路包括电流镜电路和作为差分对耦合的第一和第二晶体管。 第一输入电压被提供给第一晶体管的控制输入端。 向第二晶体管的控制输入端提供第二输入电压。 电流镜电路包括第三晶体管，耦合到第三晶体管的第四晶体管和与第四晶体管串联耦合的第五晶体管。 第三晶体管提供与通过第四晶体管的电流成比例的差分对的电流。 第四晶体管的控制输入耦合在第五晶体管和电流源之间。

公开(公告)号：US08230281B2

公开(公告)日：2012-07-24

申请号：US12422916

申请日：2009-04-13

申请人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

发明人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318572

摘要： A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

摘要翻译： 测试驱动器发射器通过电阻终端电路将测试信号驱动到第一引脚，以在边界扫描测试操作期间测试板上的组件。 在边界扫描测试操作期间，测试接收器通过第二引脚和耦合到第二引脚的通过门接收测试信号。 在环回操作期间，通过环回电路将测试信号发送到测试接收机。

公开(公告)号：US5581536A

公开(公告)日：1996-12-03

申请号：US484431

申请日：1995-06-07

申请人： Hans W. Klein ,  Sriram Narayan

发明人： Hans W. Klein ,  Sriram Narayan

IPC分类号： G11B5/596 ,  G11B7/09 ,  G11B15/60 ,  G11B17/34 ,  G11B21/10 ,  H03K5/1532 ,  G11B7/00

CPC分类号： G11B7/0901 ,  G11B21/10 ,  G11B5/59611 ,  H03K5/1532 ,  G11B15/602 ,  G11B17/34 ,  G11B7/0941

摘要： A circuit for detecting when peaks occur in an amplitude modulated electrical signal, and for measuring in real time the amplitudes of the detected peaks. The circuit delays the input signal a short time, and then notes when the input signal and its delayed version have the same amplitude, thereby to detect when a peak has occurred. The amplitude of the peak is then measured. This circuit and technique have particular advantages when used as part of a servo control system that positions a read/write head to accurately follow moving tracks of recorded data on magnetic tape, magnetic disks, optical disks, and the like.

摘要翻译： 用于检测在调幅电信号中何时发生峰值的电路，并用于实时测量检测到的峰值的振幅。 该电路在短时间内延迟输入信号，然后在输入信号及其延迟版本具有相同幅度时注意，从而检测峰值何时发生。 然后测量峰的振幅。 当用作伺服控制系统的一部分时，该电路和技术具有特别的优点，该伺服控制系统将读/写头准确地跟踪在磁带，磁盘，光盘等上的记录数据的移动轨迹。

公开(公告)号：US08594112B2

公开(公告)日：2013-11-26

申请号：US13425031

申请日：2012-03-20

申请人： Subrahmanyam Dravida ,  Sriram Narayan

发明人： Subrahmanyam Dravida ,  Sriram Narayan

IPC分类号： H04L12/56

CPC分类号： H04L49/901 ,  H04L47/14 ,  H04L47/621 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9073 ,  H04W36/02 ,  H04W36/28 ,  H04W76/20 ,  H04W88/02 ,  H04W88/08

摘要： Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. Various other aspects are also presented.

摘要翻译： 本文公开的方面解决了本领域对用于高速媒体访问控制的存储器管理的需要。 分组缓冲器可以存储具有第一数据结构的分组，包括分组长度，序列号和指向第二数据结构的指针。 分组数据可以存储在一个或多个第二数据结构的链接列表中。 发送和接收队列可以使用第一数据结构的链表或数组来形成。 用于存储第一和第二数据结构的存储器位置可以保存在指示相应数据结构类型的空闲位置的列表中。 公开了一种灵活的存储器架构，其中可以选择两种配置。 还提出了各种其他方面。