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    Two-point modulator arrangement
    1.
    发明授权
    Two-point modulator arrangement 有权
    两点调制器布置

    公开(公告)号：US07142070B2

    公开(公告)日：2006-11-28

    申请号：US10947847

    申请日：2004-09-23

    申请人： Stefan Herzinger ,  Günter Märzinger ,  Burkhard Neurauter ,  Robert Weigel

    发明人： Stefan Herzinger ,  Günter Märzinger ,  Burkhard Neurauter ,  Robert Weigel

    IPC分类号： H03C3/06

    CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

    摘要： A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

    摘要翻译： 指定了两点调制器布置，所述布置相对于传统的两点调制器被展开，使得包括锁相环的调制器的高通耦合点由扩展环路滤波器形成。 根据本原理，扩展环路滤波器包括耦合入元件，其中调制信号与相位比较器的输出信号组合。 因此，可以有利地使用仅具有一个调谐输入的压控振荡器。

    Two-point modulator arrangement
    2.
    发明申请
    Two-point modulator arrangement 有权
    两点调制器布置

    公开(公告)号：US20050104669A1

    公开(公告)日：2005-05-19

    申请号：US10947847

    申请日：2004-09-23

    申请人： Stefan Herzinger ,  Gunter Marzinger ,  Burkhard Neurauter ,  Robert Weigel

    发明人： Stefan Herzinger ,  Gunter Marzinger ,  Burkhard Neurauter ,  Robert Weigel

    IPC分类号： H03C3/09 ,  H03L7/00

    CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

    摘要： A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

    摘要翻译： 指定了两点调制器布置，所述布置相对于传统的两点调制器被展开，使得包括锁相环的调制器的高通耦合点由扩展环路滤波器形成。 根据本原理，扩展环路滤波器包括耦合入元件，其中调制信号与相位比较器的输出信号组合。 因此，可以有利地使用仅具有一个调谐输入的压控振荡器。

    Phase locked loop and method for phase correction of a frequency controllable oscillator
    3.
    发明授权
    Phase locked loop and method for phase correction of a frequency controllable oscillator 有权
    锁相环和频率可控振荡器相位校正方法

    公开(公告)号：US07391270B2

    公开(公告)日：2008-06-24

    申请号：US11086039

    申请日：2005-03-22

    申请人： Burkhard Neurauter ,  Günter Märzinger ,  Christian Münker ,  Roland Vuketich

    发明人： Burkhard Neurauter ,  Günter Märzinger ,  Christian Münker ,  Roland Vuketich

    IPC分类号： H03L7/00

    CPC分类号： H03L7/1974

    摘要： A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

    摘要翻译： 公开了一种锁相环，并且包括在反馈路径中具有可设置的分频比的分频器电路。 使用控制电路产生分频比，除了用于提供要被设置的分频比的整数和分数分量的输入外，还包括用于提供相位校正信号的输入。 为了产生相位校正信号，锁相环还包括相位校正装置。 相位校正信号优选地包含具有指数曲线的信号分量，并且被提供给控制电路以产生分频器电路的分频比，使得其补偿来自压控振荡器的输出信号中的相位漂移 锁相环。

    SIMPLIFIED ADAPTIVE FILTER ALGORITHM FOR THE CANCELLATION OF TX-INDUCED EVEN ORDER INTERMODULATION PRODUCTS
    4.
    发明申请
    SIMPLIFIED ADAPTIVE FILTER ALGORITHM FOR THE CANCELLATION OF TX-INDUCED EVEN ORDER INTERMODULATION PRODUCTS 审中-公开
    简化自适应滤波算法，用于取消TX诱导的即时交互产品

    公开(公告)号：US20120140685A1

    公开(公告)日：2012-06-07

    申请号：US12957612

    申请日：2010-12-01

    申请人： Christian Lederer ,  Huemer Mario ,  Stefan Herzinger ,  Gernot Hueber ,  Burkhard Neurauter ,  Andreas Mayer

    发明人： Christian Lederer ,  Huemer Mario ,  Stefan Herzinger ,  Gernot Hueber ,  Burkhard Neurauter ,  Andreas Mayer

    IPC分类号： H04B3/20 ,  G06F17/10

    CPC分类号： H04L27/3854 ,  H04L25/03057

    摘要： One embodiment of the present invention relates to an adaptive filtering apparatus comprising first and second real valued adaptive filters, respectively configured to receive an adaptive filter input signal based upon a transmission signal in a transmission path. The first real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a first intermodulation noise component (e.g., an in-phase component) in a desired signal and to cancel the estimated noise. The second real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a second intermodulation noise component (e.g., a quadrature phase component) in the desired signal and to cancel the estimated noise. Accordingly, each filter operates a real valued adaptive algorithm to cancel a noise component, thereby removing complex cross terms between the components from the adaptive filtering process.

    摘要翻译： 本发明的一个实施例涉及一种包括第一和第二实值自适应滤波器的自适应滤波装置，分别被配置为基于传输路径中的传输信号接收自适应滤波器输入信号。 第一实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第一互调噪声分量（例如，同相分量）并消除所估计的噪声。 第二实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第二互调噪声分量（例如，正交相位分量）并消除所估计的噪声。 因此，每个滤波器操作实值自适应算法以消除噪声分量，从而从自适应滤波处理中去除组件之间的复杂交叉项。

    Digital phase locked loop, method for controlling a digital phase locked loop and method for generating an oscillator signal
    6.
    发明申请
    Digital phase locked loop, method for controlling a digital phase locked loop and method for generating an oscillator signal 审中-公开
    数字锁相环，用于控制数字锁相环的方法和产生振荡信号的方法

    公开(公告)号：US20070008040A1

    公开(公告)日：2007-01-11

    申请号：US11477262

    申请日：2006-06-29

    申请人： Thomas Mayer ,  Stefan Herzinger ,  Burkhard Neurauter ,  Gunter Marzinger

    发明人： Thomas Mayer ,  Stefan Herzinger ,  Burkhard Neurauter ,  Gunter Marzinger

    IPC分类号： H03L7/085

    CPC分类号： H03L7/1976 ,  H03K23/667 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/50

    摘要： A digital phase locked loop includes a digital phase detector, a downstream digital filter and an oscillator. In addition, a frequency divider resides in a feedback path and has an actuating input for setting a divider ratio, the input of which is connected to the oscillator and the phase detector. The phase locked loop comprises a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word to the actuating input of the frequency divider. The data word is configured such that the sigma-delta modulator generates jitter in the frequency setting word, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time.

    摘要翻译： 数字锁相环包括数字相位检测器，下游数字滤波器和振荡器。 此外，分频器驻留在反馈路径中，并且具有用于设置分频比的致动输入，其输入连接到振荡器和相位检测器。 锁相环包括具有用于提供数据字的数据输入并具有用于向频率分配器的致动输入提供频率设定字的致动输出的Σ-Δ调制器。 数据字被配置为使得Σ-Δ调制器在频率设置字中产生抖动，结果是施加到相位检测器的反馈输入的信号在相对长的时间段内不是恒定的。

    Interface apparatus and method for data recovery and synchronization
    7.
    发明授权
    Interface apparatus and method for data recovery and synchronization 失效
    用于数据恢复和同步的接口设备和方法

    公开(公告)号：US07586994B2

    公开(公告)日：2009-09-08

    申请号：US11055740

    申请日：2005-02-10

    申请人： Stefan Herzinger ,  Christian Münker ,  Burkhard Neurauter

    发明人： Stefan Herzinger ,  Christian Münker ,  Burkhard Neurauter

    IPC分类号： H04L27/20

    CPC分类号： H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0018

    摘要： The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.

    摘要翻译： 本发明提供了一种用于数据恢复的接口装置，其向信号处理器提供具有第一分量和第二分量的模拟信号（应用于输入并包含符合编码的数据）。 由此，信号处理器产生连续的解调数据流。 数据流被提供给连接的延迟单元，其输出被设计为提供所存储的数据符号，并且可以通过控制输入端的信号设置其提供延迟。 该接口允许将数字调制器连接到基带单元上的模拟I / Q接口。

    Interface apparatus and method for data recovery and synchronization
    8.
    发明申请
    Interface apparatus and method for data recovery and synchronization 失效
    用于数据恢复和同步的接口设备和方法

    公开(公告)号：US20050190823A1

    公开(公告)日：2005-09-01

    申请号：US11055740

    申请日：2005-02-10

    申请人： Stefan Herzinger ,  Christian Munker ,  Burkhard Neurauter

    发明人： Stefan Herzinger ,  Christian Munker ,  Burkhard Neurauter

    IPC分类号： H04B1/38 ,  H04L7/033 ,  H04L27/00 ,  H04L29/10

    CPC分类号： H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0018

    摘要： The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.

    摘要翻译： 本发明提供了一种用于数据恢复的接口装置，其向信号处理器提供具有第一分量和第二分量的模拟信号（应用于输入并包含符合编码的数据）。 由此，信号处理器产生连续的解调数据流。 数据流被提供给连接的延迟单元，其输出被设计为提供所存储的数据符号，并且可以通过控制输入端的信号设置其提供延迟。 该接口允许将数字调制器连接到基带单元上的模拟I / Q接口。

    Phase locked loop and method for phase correction of a frequency controllable oscillator
    9.
    发明申请
    Phase locked loop and method for phase correction of a frequency controllable oscillator 有权
    锁相环和频率可控振荡器相位校正方法

    公开(公告)号：US20060082417A1

    公开(公告)日：2006-04-20

    申请号：US11086039

    申请日：2005-03-22

    申请人： Burkhard Neurauter ,  Gunter Marzinger ,  Christian Munker ,  Roland Vuketich

    发明人： Burkhard Neurauter ,  Gunter Marzinger ,  Christian Munker ,  Roland Vuketich

    IPC分类号： H03L7/00

    CPC分类号： H03L7/1974

    摘要： A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

    摘要翻译： 公开了一种锁相环，并且包括在反馈路径中具有可设置的分频比的分频器电路。 使用控制电路产生分频比，除了用于提供要被设置的分频比的整数和分数分量的输入外，还包括用于提供相位校正信号的输入。 为了产生相位校正信号，锁相环还包括相位校正装置。 相位校正信号优选地包含具有指数曲线的信号分量，并且被提供给控制电路以产生分频器电路的分频比，使得其补偿来自压控振荡器的输出信号中的相位漂移 锁相环。