公开(公告)号：US20050104669A1

公开(公告)日：2005-05-19

申请号：US10947847

申请日：2004-09-23

申请人： Stefan Herzinger ,  Gunter Marzinger ,  Burkhard Neurauter ,  Robert Weigel

发明人： Stefan Herzinger ,  Gunter Marzinger ,  Burkhard Neurauter ,  Robert Weigel

IPC分类号： H03C3/09 ,  H03L7/00

CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

摘要： A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

摘要翻译： 指定了两点调制器布置，所述布置相对于传统的两点调制器被展开，使得包括锁相环的调制器的高通耦合点由扩展环路滤波器形成。 根据本原理，扩展环路滤波器包括耦合入元件，其中调制信号与相位比较器的输出信号组合。 因此，可以有利地使用仅具有一个调谐输入的压控振荡器。

公开(公告)号：US20070008040A1

公开(公告)日：2007-01-11

申请号：US11477262

申请日：2006-06-29

申请人： Thomas Mayer ,  Stefan Herzinger ,  Burkhard Neurauter ,  Gunter Marzinger

发明人： Thomas Mayer ,  Stefan Herzinger ,  Burkhard Neurauter ,  Gunter Marzinger

IPC分类号： H03L7/085

CPC分类号： H03L7/1976 ,  H03K23/667 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/50

摘要： A digital phase locked loop includes a digital phase detector, a downstream digital filter and an oscillator. In addition, a frequency divider resides in a feedback path and has an actuating input for setting a divider ratio, the input of which is connected to the oscillator and the phase detector. The phase locked loop comprises a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word to the actuating input of the frequency divider. The data word is configured such that the sigma-delta modulator generates jitter in the frequency setting word, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time.

摘要翻译： 数字锁相环包括数字相位检测器，下游数字滤波器和振荡器。 此外，分频器驻留在反馈路径中，并且具有用于设置分频比的致动输入，其输入连接到振荡器和相位检测器。 锁相环包括具有用于提供数据字的数据输入并具有用于向频率分配器的致动输入提供频率设定字的致动输出的Σ-Δ调制器。 数据字被配置为使得Σ-Δ调制器在频率设置字中产生抖动，结果是施加到相位检测器的反馈输入的信号在相对长的时间段内不是恒定的。

公开(公告)号：US20060114071A1

公开(公告)日：2006-06-01

申请号：US11141591

申请日：2005-05-31

申请人： Stefan Herzinger ,  Gunter Marzinger

发明人： Stefan Herzinger ,  Gunter Marzinger

IPC分类号： H03L7/00

CPC分类号： H03C3/0983 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0975 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked loop. The feedback path includes a frequency divider that connects the oscillator output to the phase detector. The phase locked loop further includes an integrator-free loop filter configured to control the oscillator. The integrator-free loop filter enables a reduction in the required PLL bandwidth without reducing the signal quality when the PLL is used as a modulator.

摘要翻译： 公开了具有正向路径和反馈路径的锁相环PLL。 相位检测器驱动锁相环的正向路径中的振荡器。 反馈路径包括将振荡器输出连接到相位检测器的分频器。 锁相环还包括被配置为控制振荡器的无积分器环路滤波器。 无需集成器的环路滤波器可以在PLL用作调制器时降低所需的PLL带宽，而不会降低信号质量。

公开(公告)号：US09112476B2

公开(公告)日：2015-08-18

申请号：US13405673

申请日：2012-02-27

申请人： Umut Basaran ,  Josef Schmal ,  Stefan Herzinger ,  Herbert Stockinger ,  Volker Thomas

发明人： Umut Basaran ,  Josef Schmal ,  Stefan Herzinger ,  Herbert Stockinger ,  Volker Thomas

IPC分类号： H04B1/38 ,  H03H7/12 ,  H03H11/12 ,  H04B1/525 ,  H03H7/01

CPC分类号： H03H7/0153 ,  H03H7/06 ,  H03H7/12 ,  H03H11/1217 ,  H03H2007/013 ,  H04B1/525

摘要： The disclosed invention relates to a transceiver system comprising a notch filter element configured to suppress transmitter blockers (i.e., transmitter interferer signals) within a reception path. In some embodiments, the transceiver front-end comprises a differential reception path, having a first differential branch and a second differential branch, configured to provide an RF differential input signal having a transmitter blocker to a transimpedance amplifier, comprising a first-order active filter and a notch filter element. The notch filter element comprises a stop band corresponding to a frequency of a transmitted signal, such that the notch filter element suppresses the transmitted blocker without degrading the signal quality of the received differential input signal.

摘要翻译： 所公开的本发明涉及一种收发器系统，包括陷波滤波器元件，其被配置为抑制接收路径内的发射机阻挡器（即，发射机干扰信号）。 在一些实施例中，收发机前端包括具有第一差分支路和第二差分支路的差分接收路径，其被配置为向跨阻抗放大器提供具有发射机阻断器的RF差分输入信号，包括一阶有源滤波器 和陷波滤波器元件。 陷波滤波器元件包括对应于发送信号的频率的阻带，使得陷波滤波器元件抑制所发送的阻断器而不降低接收的差分输入信号的信号质量。

公开(公告)号：US07205849B2

公开(公告)日：2007-04-17

申请号：US11141591

申请日：2005-05-31

申请人： Stefan Herzinger ,  Günter Märzinger

发明人： Stefan Herzinger ,  Günter Märzinger

IPC分类号： H03L7/085 ,  H03L7/093

CPC分类号： H03C3/0983 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0975 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked loop. The feedback path includes a frequency divider that connects the oscillator output to the phase detector. The phase locked loop further includes an integrator-free loop filter configured to control the oscillator. The integrator-free loop filter enables a reduction in the required PLL bandwidth without reducing the signal quality when the PLL is used as a modulator.

摘要翻译： 公开了具有正向路径和反馈路径的锁相环PLL。 相位检测器驱动锁相环的正向路径中的振荡器。 反馈路径包括将振荡器输出连接到相位检测器的分频器。 锁相环还包括被配置为控制振荡器的无积分器环路滤波器。 无需集成器的环路滤波器可以在PLL用作调制器时降低所需的PLL带宽，而不会降低信号质量。

公开(公告)号：US07982547B2

公开(公告)日：2011-07-19

申请号：US12414575

申请日：2009-03-30

申请人： Stefan Herzinger

发明人： Stefan Herzinger

IPC分类号： H03L7/24

CPC分类号： H03L7/0812 ,  H03J3/20 ,  H03J2200/08

摘要： Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.

摘要翻译： 公开了一种可调滤波器的基于锁相环的频率调谐。 谐振电路包括可调滤波器，并且振荡器信号为谐振电路提供输入。

公开(公告)号：US07777578B2

公开(公告)日：2010-08-17

申请号：US11394013

申请日：2006-03-30

申请人： Alexander Belitzer ,  Stefan Herzinger ,  Giuseppe Li Puma

发明人： Alexander Belitzer ,  Stefan Herzinger ,  Giuseppe Li Puma

IPC分类号： H03L7/085

CPC分类号： H03L7/00 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124

摘要： An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The oscillator circuit contains a phase delay circuit having a switching input, a clock signal input which is coupled to the output of the rectifier circuit, and a switching output coupled to the switching device. The phase delay circuit has a comparison circuit for comparison of a phase of the clock signal that is applied to the signal input with a reference phase. This phase delay circuit is designed to emit a switching signal after application of an activation signal to the switching input and after the phase of the clock signal which is applied to the signal input matches the reference phase. In consequence, the switching process is delayed until the step-function response of the output signal of the oscillator does not cause a sudden phase change in the clock signal.

摘要翻译： 公开了可调谐到离散值的振荡器，并且包括可经由开关装置连接的调谐元件。 整流电路连接到振荡器的输出端并形成来自振荡器信号的时钟信号。 振荡器电路包括具有开关输入的相位延迟电路，耦合到整流器电路的输出的时钟信号输入和耦合到开关器件的开关输出。 相位延迟电路具有用于比较施加到具有参考相位的信号输入的时钟信号的相位的比较电路。 该相位延迟电路被设计成在施加到开关输入的激活信号之后并且在施加到信号输入的时钟信号的相位与参考相位匹配之后发出切换信号。 因此，切换过程被延迟，直到振荡器的输出信号的阶跃函数响应不会引起时钟信号的突然相位变化。

公开(公告)号：US20070286314A1

公开(公告)日：2007-12-13

申请号：US11753728

申请日：2007-05-25

申请人： Stefan Herzinger ,  Andreas Menkhoff ,  Stefan Meier ,  Norbert Neurohr

发明人： Stefan Herzinger ,  Andreas Menkhoff ,  Stefan Meier ,  Norbert Neurohr

IPC分类号： H04L27/06 ,  H04L7/00

CPC分类号： H04L7/042

摘要： A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

摘要翻译： 公开了一种方法，包括识别帧中的前同步码，其中前导码具有前同步码长度1。 连续接收的M个数据项被存储。 m个数据项一次划分为n个部分，其中每个部分中的数据项分别在连续的时间被接收，并且其中m和n是自然数，并且以下适用于m和n：m> n，m> 1，n > 1。 n个部分分别与预期值相关以形成分量相关结果。 延迟分量相关结果，至少两个分量相关结果被不同长度延迟。 该方法还包括组合延迟分量相关结果以形成总相关值。 总相关值用于确定m个接收的数据项是否包含帧的前同步码。

公开(公告)号：US20120140685A1

公开(公告)日：2012-06-07

申请号：US12957612

申请日：2010-12-01

申请人： Christian Lederer ,  Huemer Mario ,  Stefan Herzinger ,  Gernot Hueber ,  Burkhard Neurauter ,  Andreas Mayer

发明人： Christian Lederer ,  Huemer Mario ,  Stefan Herzinger ,  Gernot Hueber ,  Burkhard Neurauter ,  Andreas Mayer

IPC分类号： H04B3/20 ,  G06F17/10

CPC分类号： H04L27/3854 ,  H04L25/03057

摘要： One embodiment of the present invention relates to an adaptive filtering apparatus comprising first and second real valued adaptive filters, respectively configured to receive an adaptive filter input signal based upon a transmission signal in a transmission path. The first real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a first intermodulation noise component (e.g., an in-phase component) in a desired signal and to cancel the estimated noise. The second real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a second intermodulation noise component (e.g., a quadrature phase component) in the desired signal and to cancel the estimated noise. Accordingly, each filter operates a real valued adaptive algorithm to cancel a noise component, thereby removing complex cross terms between the components from the adaptive filtering process.

摘要翻译： 本发明的一个实施例涉及一种包括第一和第二实值自适应滤波器的自适应滤波装置，分别被配置为基于传输路径中的传输信号接收自适应滤波器输入信号。 第一实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第一互调噪声分量（例如，同相分量）并消除所估计的噪声。 第二实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第二互调噪声分量（例如，正交相位分量）并消除所估计的噪声。 因此，每个滤波器操作实值自适应算法以消除噪声分量，从而从自适应滤波处理中去除组件之间的复杂交叉项。

公开(公告)号：US07280617B2

公开(公告)日：2007-10-09

申请号：US10734707

申请日：2003-12-11

申请人： Michael Cujé ,  Stefan Eibl ,  Stefan Herzinger ,  Martin Krüger ,  Xiaofeng Wu ,  Bin Yang

发明人： Michael Cujé ,  Stefan Eibl ,  Stefan Herzinger ,  Martin Krüger ,  Xiaofeng Wu ,  Bin Yang

IPC分类号： H04L25/10

CPC分类号： H04B1/30

摘要： In a method to compensate for a step DC disturbance (1) in a baseband signal in a homodyne radio receiver, the time profile of the step DC disturbance within a burst is determined. In order to produce a step-corrected baseband signal, the determined time profile (2) is then calculated from the digitized baseband signal.

摘要翻译： 在补偿在零差无线电接收机中的基带信号中的步进DC干扰（1）的方法中，确定突发内的步骤DC干扰的时间曲线。 为了产生步进校正的基带信号，则从数字化的基带信号计算确定的时间分布（2）。