公开(公告)号：US07062640B2

公开(公告)日：2006-06-13

申请号：US09735899

申请日：2000-12-14

申请人： Stephan J. Jourdan ,  Alan Miller ,  Glenn Hinton

发明人： Stephan J. Jourdan ,  Alan Miller ,  Glenn Hinton

IPC分类号： G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F12/0888

摘要： A filtering system for instruction segments determines whether a new instruction segment satisfies a predetermined filtering condition prior to storage. If the instruction segment fails the filtering condition, the new instruction segment is not stored. Various filtering conditions are available; but all filtering conditions test to determine whether it is more likely than not that a new instruction segment will be reused by the execution unit in the future.

公开(公告)号：US07143273B2

公开(公告)日：2006-11-28

申请号：US10404812

申请日：2003-03-31

申请人： John Alan Miller ,  Slade A. Morgan ,  Stephan J. Jourdan

发明人： John Alan Miller ,  Slade A. Morgan ,  Stephan J. Jourdan

IPC分类号： G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3848

摘要： Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.

摘要翻译： 在从跟踪高速缓存中读取跟踪并且可重复访问全局历史记录中访问跟踪高速缓存中的指令的排序所暗示的由分支预测创建的炖菜时，切换全局历史记录中的条目 读取跟踪高速缓冲存储器内的跟踪内的分支指令多于一条第二分支指令时，炖菜的变化。

公开(公告)号：US06898699B2

公开(公告)日：2005-05-24

申请号：US10029128

申请日：2001-12-21

申请人： Stephan J. Jourdan ,  John Alan Miller ,  Namratha Jaisimha

发明人： Stephan J. Jourdan ,  John Alan Miller ,  Namratha Jaisimha

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3808 ,  G06F9/30054 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3842 ,  G06F9/3848

摘要： An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.

摘要翻译： 一种用于存储由流水线处理器执行的指令的预测返回地址的装置，该装置包括两部分返回地址缓冲器，其包括推测返回地址缓冲器和承诺返回地址缓冲器，两者都具有可包括预测返回的多个条目 被推送到返回缓冲区的地址。

公开(公告)号：US07181598B2

公开(公告)日：2007-02-20

申请号：US10146956

申请日：2002-05-17

申请人： Stephan J. Jourdan ,  Darrell D. Boggs ,  John Alan Miller ,  Ronak Singhal

发明人： Stephan J. Jourdan ,  Darrell D. Boggs ,  John Alan Miller ,  Ronak Singhal

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3857

摘要： In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

摘要翻译： 在处理核心中，新接收的加载指令可以取决于先前接收的存储指令。 核心可以包括预测这种依赖性的预测器，并提供碰撞存储指令的标识。 加载指令可以存储在具有依赖标记的调度器中。 此后，可以防止加载指令在执行冲突存储之前执行。 在执行负载时，确认预测的精度。 在加载指令退出后，可以向预测器提供新的预测结果。

公开(公告)号：US20110060931A1

公开(公告)日：2011-03-10

申请号：US12557263

申请日：2009-09-10

申请人： SIVAKUMAR RADHAKRISHNAN ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Lool ,  Yi-Feng Liu

发明人： SIVAKUMAR RADHAKRISHNAN ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Lool ,  Yi-Feng Liu

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

摘要翻译： 一种能够以各种模式对片上系统进行功率测量的方法和系统。 在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。 这允许钩子或接口在外部访问片上系统进行测量。 例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量， 片上 片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。 另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

公开(公告)号：US07797683B2

公开(公告)日：2010-09-14

申请号：US10745527

申请日：2003-12-29

申请人： Per H. Hammarlund ,  Stephan J. Jourdan ,  Pierre Michaud ,  Alexandre J. Farcy ,  Morris Marden ,  Robert L. Hinton ,  Douglas M. Carmean

发明人： Per H. Hammarlund ,  Stephan J. Jourdan ,  Pierre Michaud ,  Alexandre J. Farcy ,  Morris Marden ,  Robert L. Hinton ,  Douglas M. Carmean

IPC分类号： G06F9/44

CPC分类号： G06F9/485 ,  G06F9/3851

摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

摘要翻译： 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。 可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。 逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。 也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。 在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

公开(公告)号：US07644236B2

公开(公告)日：2010-01-05

申请号：US11045528

申请日：2005-01-28

申请人： Adi Yoaz ,  Ronny Ronen ,  Lihu Rappoport ,  Mattan Erez ,  Stephan J. Jourdan ,  Bob Valentine

发明人： Adi Yoaz ,  Ronny Ronen ,  Lihu Rappoport ,  Mattan Erez ,  Stephan J. Jourdan ,  Bob Valentine

IPC分类号： G06F12/00

CPC分类号： G06F9/3885 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3836 ,  G06F12/0846

摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

摘要翻译： 提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。 存储器缓存库预测单元具有接收指令的输入端口。 存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

公开(公告)号：US07502912B2

公开(公告)日：2009-03-10

申请号：US10749272

申请日：2003-12-30

申请人： Avinash Sodani ,  Per H. Hammarlund ,  Stephan J. Jourdan

发明人： Avinash Sodani ,  Per H. Hammarlund ,  Stephan J. Jourdan

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861

摘要： A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.

摘要翻译： 一种用于在处理器中重新调度操作的方法和装置。 更具体地说，本发明涉及通过分析，预测和排序指令的写入顺序来最优化地使用处理器中的调度器资源，使得指令在调度器中空闲的持续时间最小化。 分析，预测和排序可以通过使用延迟单元在指令队列和调度器之间完成。 预测可以基于历史（延迟，依赖和资源）或一般预测方案。

公开(公告)号：US07444457B2

公开(公告)日：2008-10-28

申请号：US10743285

申请日：2003-12-23

申请人： Stephan J. Jourdan ,  Chris E. Yunker ,  Pierre Michaud

发明人： Stephan J. Jourdan ,  Chris E. Yunker ,  Pierre Michaud

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/383 ,  G06F12/0864

摘要： Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.

摘要翻译： 处理地址的系统和方法提供用于接收指令的完整线性地址并减小全线性地址的大小以获得减小的线性地址。 如果减少的线性地址对应于标签阵列中的标签，其中标签阵列与数据阵列相关联，则可以从数据阵列检索数据块。 缩小的线性地址可使标签阵列的尺寸更小或实现增强的性能。 数据阵列可以是高速缓存的分支预测器或高速缓存阵列的预测阵列。

公开(公告)号：US07428627B2

公开(公告)日：2008-09-23

申请号：US09750150

申请日：2000-12-29

申请人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

发明人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

IPC分类号： G06F12/02

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832 ,  G06F9/3844

摘要： A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.

摘要翻译： 公开了一种具有多种预测模式的处理器的多模式预测器。 预测模式用于预测非二进制值。 预测器是包括每IP（“PIP”）表和下一个值表的多模式预测器。 PIP表包括多个PIP信息字段，下一个值表包括多个字段。 多模式预测器还包括多种预测模式。 处理器包括一组索引PIP表以提供有效信号的指令。 处理器还包括用于该组指令的一组预测值。 预测值的集合存储在PIP表和下一个值表中。 根据有效信号在下一个值表中的命中/未命中条件，从PIP表或下一个值表中选择预测值。