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    Metal-insulator-metal (MIM) device and method of formation thereof
    1.
    发明申请
    Metal-insulator-metal (MIM) device and method of formation thereof 有权
    金属绝缘体金属（MIM）器件及其形成方法

    公开(公告)号：US20090109598A1

    公开(公告)日：2009-04-30

    申请号：US11980213

    申请日：2007-10-30

    申请人： Steven Avanzino ,  Tzu-Ning Fang ,  Swaroop Kaza ,  Dongxiang Liao ,  Wai Lo ,  Christie Marrian ,  Sameer Haddad

    发明人： Steven Avanzino ,  Tzu-Ning Fang ,  Swaroop Kaza ,  Dongxiang Liao ,  Wai Lo ,  Christie Marrian ,  Sameer Haddad

    IPC分类号： H01G4/002 ,  H01G7/00

    CPC分类号： H01L28/40 ,  H01G4/10 ,  H01G13/00 ,  H01L27/101 ,  H01L28/57 ,  Y10T29/435

    摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

    摘要翻译： 在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，首先提供第一电极。 在第一电极上设置氧化物层，在氧化物层上设置保护层。 提供通过保护层的开口以暴露氧化物层的一部分，氧化层的暴露部分下方的第一电极的一部分被氧化。 提供与氧化物层的暴露部分接触的第二电极。 在替代实施例中，可以消除初始提供的氧化物层，并且可以在开口中提供绝缘材料的间隔物。

    Pin diode device and architecture
    5.
    发明授权
    Pin diode device and architecture 有权
    pin二极管器件和架构

    公开(公告)号：US07916529B2

    公开(公告)日：2011-03-29

    申请号：US12370932

    申请日：2009-02-13

    申请人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

    发明人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

    IPC分类号： G11C11/36

    CPC分类号： H01L27/1021 ,  G11C5/04 ,  G11C11/36 ,  H01L27/24 ,  H01L29/868

    摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

    摘要翻译： 提供采用一个或多个半导体PIN二极管的存储架构。 存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

    Method of programming, reading and erasing memory-diode in a memory-diode array
    9.
    发明申请
    Method of programming, reading and erasing memory-diode in a memory-diode array 有权
    在存储二极管阵列中编程，读取和擦除存储二极管的方法

    公开(公告)号：US20060139994A1

    公开(公告)日：2006-06-29

    申请号：US11021958

    申请日：2004-12-23

    申请人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    发明人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    IPC分类号： G11C11/36

    CPC分类号： G11C11/36

    摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

    摘要翻译： 存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。 在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。 在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。 每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。 通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

    Use of periodic refresh in medium retention memory arrays
    10.
    发明授权
    Use of periodic refresh in medium retention memory arrays 有权
    在介质保留存储器阵列中使用定期更新

    公开(公告)号：US07474579B2

    公开(公告)日：2009-01-06

    申请号：US11613832

    申请日：2006-12-20

    申请人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    发明人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

    摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

    摘要翻译： 公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法 跟踪元件的电阻已达到或超过预定参考阈值电阻值。 跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元 在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。