公开(公告)号：US08422270B2

公开(公告)日：2013-04-16

申请号：US13044892

申请日：2011-03-10

申请人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US08482956B2

公开(公告)日：2013-07-09

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US08120944B2

公开(公告)日：2012-02-21

申请号：US12722851

申请日：2010-03-12

申请人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

发明人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/24

摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

摘要翻译： 非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。 非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。 形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成， 要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线 检测到。

公开(公告)号：US20120014163A1

公开(公告)日：2012-01-19

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US20110228586A1

公开(公告)日：2011-09-22

申请号：US13044892

申请日：2011-03-10

申请人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US20100232209A1

公开(公告)日：2010-09-16

申请号：US12722851

申请日：2010-03-12

申请人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

发明人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/24

摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

摘要翻译： 非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。 非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。 形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成， 要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线 检测到。

公开(公告)号：US20100118592A1

公开(公告)日：2010-05-13

申请号：US12611279

申请日：2009-11-03

申请人： Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

发明人： Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2216/22

摘要： Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device comprises: a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix; a row decoder shared by the first sub-bank and the second sub-bank; a first column decoder and a second column decoder provided in the first sub-bank and the second sub-bank, respectively; and a control circuit arranged to execute alternately a first action cycle to perform a programming action in the first sub-bank and a reading action for a programming verifying action in the second sub-bank and a second action cycle to perform the reading action for the programming verifying action in the first sub-bank and the programming action in the second sub-bank.

摘要翻译： 提供了一种能够高速地对存储单元执行写入动作的非易失性半导体存储器件。 该装置包括：具有第一子库和第二子库的存储单元阵列，每个具有以矩阵形式布置的多个非易失性存储单元; 由第一子银行和第二子银行共享的行解码器; 分别设置在第一子行和第二子行中的第一列解码器和第二列解码器; 以及控制电路，被配置为交替地执行第一动作循环以在第一子存储体中执行编程动作，以及执行用于第二子存储体中的编程验证动作的读取动作和第二动作循环，以执行对于第二子存储体的读取动作 在第一子行中编程验证动作和第二子行中的编程动作。

公开(公告)号：US20120075909A1

公开(公告)日：2012-03-29

申请号：US13212457

申请日：2011-08-18

申请人： Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

发明人： Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/79

摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

摘要翻译： 提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。 无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲 电阻值被应用。 此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。 通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

公开(公告)号：US08737115B2

公开(公告)日：2014-05-27

申请号：US13478498

申请日：2012-05-23

申请人： Shinobu Yamazaki ,  Kazuya Ishihara ,  Suguru Kawabata

发明人： Shinobu Yamazaki ,  Kazuya Ishihara ,  Suguru Kawabata

IPC分类号： G11C13/00 ,  G11C11/16

CPC分类号： G11C13/0069 ,  G11C11/16 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/32 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/146

摘要： A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.

摘要翻译： 提供了一种与可变电阻元件的形成处理方法相比，其在与开关动作中的脉冲形成和写入电流相当的短时间内进行，与DC形成相同。 在形成过程中，可变电阻元件由刚刚产生的初始高电阻状态的电压脉冲施加到执行开关动作的可变电阻状态而改变。 该形成工艺包括将可变电阻元件的电阻降低的电压幅度低于阈值电压的第一脉冲施加到可变电阻元件的两个电极之间的第一步骤， 在第一步骤之后具有与第一脉冲具有相同极性且不低于阈值电压的电压振幅的第二脉冲。

公开(公告)号：US20110292715A1

公开(公告)日：2011-12-01

申请号：US13114507

申请日：2011-05-24

申请人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

发明人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

IPC分类号： G11C11/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

摘要翻译： 半导体存储器件包括其中多个存储器单元以矩阵形状排列的存储单元阵列，每个存储单元包括串联连接的两端存储元件和选择晶体管; 对第一位线施加写入电压脉冲的第一电压施加电路; 以及施加预充电电压到第一位线和第二位线的第二电压施加电路，其中在存储单元的写入中，在所述第二电压施加电路将所述存储器单元的两端预充电到 第一电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲用于选择，并且第二电压施加电路将预充电电压施加到直接连接到存储器的第二位线 元件。