公开(公告)号：US20050224147A1

公开(公告)日：2005-10-13

申请号：US10986458

申请日：2004-11-12

申请人： Sung Jung ,  Hong Lee ,  Jong Son ,  Chang Pak

发明人： Sung Jung ,  Hong Lee ,  Jong Son ,  Chang Pak

IPC分类号： C06B35/00 ,  C06B45/32 ,  C06C7/00

CPC分类号： C06B45/32 ,  C06C7/00

摘要： The present invention relates to a non-toxic primer powder composition for small caliber ammunition characterized by comprising potassium nitrate coated with shellac as an oxidizer, and particularly characterized by comprising 25-40 wt % of an initiating explosive, 10-30 wt % of nitrate ester as a fuel, 32-40 wt % of a shellac-coated potassium nitrate (KNO3) as an oxidizer, 5-10 wt % of tetracene as a first sensitizer, 3-9 wt % of a borosilicate powder as a second sensitizer and 0.1-0.2 wt % of a chemical binder.

摘要翻译： 本发明涉及一种用于小口径弹药的无毒底漆粉末组合物，其特征在于包含用虫胶涂覆的硝酸钾作为氧化剂，其特征在于包含25-40重量％的起始炸药，10-30重量％的硝酸盐 酯作为燃料，32-40重量％的作为氧化剂的虫胶涂覆的硝酸钾（KNO 3 N 3），5-10重量％的并四苯作为第一敏化剂，3-9重量％的 作为第二敏化剂的硼硅酸盐粉末和0.1-0.2重量％的化学粘合剂。

公开(公告)号：US20070131996A1

公开(公告)日：2007-06-14

申请号：US11701484

申请日：2007-02-02

申请人： Sung Jung ,  Jum Kim

发明人： Sung Jung ,  Jum Kim

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.

公开(公告)号：US20060228581A1

公开(公告)日：2006-10-12

申请号：US11240633

申请日：2005-10-03

申请人： Jeong Seo ,  Chun Park ,  Soon Kwon ,  Yun Kim ,  Sung Jung ,  Jun Ahn ,  Hyung Kim

发明人： Jeong Seo ,  Chun Park ,  Soon Kwon ,  Yun Kim ,  Sung Jung ,  Jun Ahn ,  Hyung Kim

IPC分类号： H01L51/54 ,  H05B33/14 ,  C09K11/06

CPC分类号： C07F15/0033 ,  C09K11/06 ,  C09K2211/1029 ,  C09K2211/185 ,  H01L51/0085 ,  H01L51/0094 ,  H01L51/5012 ,  H05B33/14 ,  Y10S428/917

摘要： Disclosed are iridium-based luminescent compounds having phenylpyridine moieties with an organosilicon group, and organic electroluminescence devices using the compounds as color-producing materials. The luminescent compounds have the structure of Formula 1 below: wherein L1, L2, L3, R1, R2 and R3, which may be identical to or different from each other, are each independently selected from the group consisting of aryl, alkoxy, alkyl, and groups of Formulae 2 and 3 below: wherein D1, D2 and D3 are each independently selected from the group consisting of C1˜18 alkyl, C1˜18 alkoxy, substituted or unsubstituted C1˜18 alkyl and allyl, and substituted or unsubstituted C6˜18 fluorinated alkyl and allyl groups; wherein D4, D5 and D6 are each independently selected from the group consisting of C1˜18 alkyl, C1˜18 alkoxy, substituted or unsubstituted C1˜18 alkyl and allyl, and substituted or unsubstituted C6˜18 fluorinated alkyl and allyl groups.

摘要翻译： 公开了具有有机硅基团的苯基吡啶部分的铱系发光化合物和使用该化合物作为生色材料的有机电致发光器件。 发光化合物具有以下式1的结构：其中L 1，L 2，L 3，R 1，N 2， R 2，R 3和R 3可以彼此相同或不同，各自独立地选自芳基，烷氧基，烷基和基团 下式2和3的化合物：其中D 1，D 2和D 3各自独立地选自C 1 -C 6烷基， 1〜18个烷基，C 1〜18个烷氧基，取代或未取代的C 1-18烷基和烯丙基，以及取代或未取代的C 6〜 18 氟烷基和烯丙基; 其中D 4，D 5和D 6各自独立地选自C 1〜18， 烷基，C 1〜18烷氧基，取代或未取代的C 1-18烷基和烯丙基，以及取代或未取代的C 6-18烷氧基烷基 和烯丙基。

公开(公告)号：US20050142745A1

公开(公告)日：2005-06-30

申请号：US11019302

申请日：2004-12-23

申请人： Sung Jung ,  Jum Kim

发明人： Sung Jung ,  Jum Kim

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.

摘要翻译： 本发明提供了一种闪速存储器件中的沟槽隔离方法，通过这种方法，在沟槽隔离层的边缘附近形成厚的衬垫氧化物层，增强了器件的稳定性和可靠性。 本发明包括在半导体衬底上形成掩模层图案以暴露器件隔离区域而覆盖其有效区域，掩模层图案包括第一绝缘层图案和叠置在其上的第二绝缘层图案，形成沟槽 所述半导体衬底对应于所述器件隔离区域，去除所述第一绝缘层图案的暴露部分以足以暴露所述半导体衬底在与所述沟槽相邻的有源区域中的一部分，在所述沟槽的内部形成侧壁氧化物层，以及 半导体衬底的暴露部分，用第三绝缘层填充沟槽以覆盖侧壁氧化物层，以及去除掩模层图案。

公开(公告)号：US20050139916A1

公开(公告)日：2005-06-30

申请号：US11020276

申请日：2004-12-27

申请人： Jum Kim ,  Sung Jung

发明人： Jum Kim ,  Sung Jung

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/41775

摘要： A high voltage semiconductor device and fabricating method thereof, enable a high breakdown voltage to be provided from a surface area without forming a dual spacer layer. The semiconductor device includes a semiconductor substrate having source/drain regions separated from each other by a channel region in-between, a gate insulating layer pattern on the channel region, a gate conductor layer pattern on the gate insulating layer, a sidewall insulating layer provided on a sidewall of the gate conductor layer pattern, a salicide suppress layer pattern covering partial, but not entire, surfaces of the source/drain regions, and covering the sidewall insulating layer, and the gate conductor layer pattern, and a metal salicide layer on remaining portions surfaces of the source/drain regions that are not covered with the salicide suppress layer pattern.

摘要翻译： 高压半导体器件及其制造方法能够从表面区域提供高的击穿电压而不形成双间隔层。 半导体器件包括具有源极/漏极区域的半导体衬底，沟道区域之间的沟道区域彼此分离，沟道区域上的栅极绝缘层图案，栅极绝缘层上的栅极导体层图案，提供的侧壁绝缘层 在栅极导体层图案的侧壁上，覆盖源极/漏极区域的部分但不是整个表面并且覆盖侧壁绝缘层和栅极导体层图案以及金属硅化物层的自对准硅化物抑制层图案 未被自对准硅化物抑制层图案覆盖的源/漏区的剩余部分表面。

公开(公告)号：US20050087793A1

公开(公告)日：2005-04-28

申请号：US10969995

申请日：2004-10-22

申请人： Sung Jung ,  Dong Kim

发明人： Sung Jung ,  Dong Kim

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A low density and cost effective embedded non-volatile memory cell includes a semiconductor substrate of a first conductivity type and having device isolation regions and active regions defined therein; a first well of a second conductivity type in the semiconductor substrate; a plurality of second wells of the first conductivity type inside the first well, the second wells being formed in parallel with a bit line and surrounded by the device isolation regions and the first well; a plurality of ONO structures formed over corresponding ones of the second wells, each ONO structure including a first oxide film, a nitride film, and a second oxide film; and a plurality of gates formed on corresponding ones of the ONO structures and formed in parallel with a word line.

摘要翻译： 低密度和成本有效的嵌入式非易失性存储单元包括第一导电类型的半导体衬底并且具有限定在其中的器件隔离区和有源区; 半导体衬底中的第二导电类型的第一阱; 第一阱中的第一导电类型的多个第二阱，第二阱与位线并联形成并被器件隔离区和第一阱围绕; 在对应的第二阱上形成的多个ONO结构，每个ONO结构包括第一氧化膜，氮化物膜和第二氧化物膜; 以及形成在对应的ONO结构上并与字线平行形成的多个门。

公开(公告)号：US20050075507A1

公开(公告)日：2005-04-07

申请号：US10608709

申请日：2003-06-27

申请人： Il Cho ,  Hyun Park ,  Ji Noh ,  Hyung Ryu ,  Sang Park ,  Sung Jung ,  Sung Lee ,  Jong Kim ,  Jee Lim ,  Chun Lyu ,  Dal Kim ,  Young Kim ,  Kyu Yeon ,  Myeong Chae ,  In Min ,  Hae Jin ,  Kyoung Kang

发明人： Il Cho ,  Hyun Park ,  Ji Noh ,  Hyung Ryu ,  Sang Park ,  Sung Jung ,  Sung Lee ,  Jong Kim ,  Jee Lim ,  Chun Lyu ,  Dal Kim ,  Young Kim ,  Kyu Yeon ,  Myeong Chae ,  In Min ,  Hae Jin ,  Kyoung Kang

IPC分类号： C07D249/10 ,  A61P29/00 ,  C07D249/08 ,  C07D401/04 ,  C07D403/04 ,  C07D405/04

CPC分类号： C07D249/08 ,  C07C311/39 ,  C07C323/36 ,  C07D213/77 ,  C07D237/20 ,  C07D401/04 ,  C07D403/04 ,  C07D405/04

摘要： A 1,2,4-Triazole derivative of formula 1 or a non-toxic salt thereof, a preparation method thereof, and a pharmaceutical composition containing the derivative or the salt as an active ingredient are provided.

摘要翻译： 提供式1的1,2,4-三唑衍生物或其无毒盐，其制备方法和含有该衍生物或盐作为有效成分的药物组合物。

公开(公告)号：US20070153159A1

公开(公告)日：2007-07-05

申请号：US11398561

申请日：2006-04-06

申请人： Sung Jung

发明人： Sung Jung

IPC分类号： G02F1/1335

CPC分类号： G02B6/0073 ,  G02B6/0068 ,  G02B6/009 ,  G02F1/133603 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2924/00014

摘要： Provided is a light emitting diode array including: a plurality of light emitting chips spaced apart from one another by a predetermined distance; and a fixing member that positions the plurality of light emitting chips at predetermined heights and/or predetermined directions. Also provided are methods for manufacturing the light emitting diode array, a backlight assembly including the light emitting diode array, and a liquid crystal display device including the light emitting diode array.

摘要翻译： 提供了一种发光二极管阵列，包括：多个发光芯片彼此间隔开预定距离; 以及固定构件，其将所述多个发光芯片定位在预定高度和/或预定方向。 还提供了制造发光二极管阵列的方法，包括发光二极管阵列的背光组件和包括发光二极管阵列的液晶显示装置。

公开(公告)号：US20070148959A1

公开(公告)日：2007-06-28

申请号：US11616808

申请日：2006-12-27

申请人： Sung Jung

发明人： Sung Jung

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/4763

CPC分类号： H01L21/76832

摘要： Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device having a pre-metal dielectric liner. In embodiments, method for forming a semiconductor device may include forming a pre-metal dielectric liner, which has a multi-layer structure including a plurality of interfacial surfaces, on an entire surface of a semiconductor substrate formed with a transistor, and forming a boron phospho silicate glass (BPSG) oxide layer on the pre-metal dielectric liner. Since the pre-metal dielectric liner is formed in a multi-layer structure having a plurality of interfacial surfaces, boron (B) of an upper BPSG oxide layer is not penetrated into the semiconductor substrate.

摘要翻译： 实施例涉及半导体器件和制造具有预金属电介质衬垫的半导体器件的方法。 在实施例中，用于形成半导体器件的方法可以包括在形成有晶体管的半导体衬底的整个表面上形成具有包括多个界面的多层结构的预金属电介质衬垫，并形成硼 磷酸硅玻璃（BPSG）氧化物层在预金属电介质衬垫上。 由于预金属电介质衬垫形成为具有多个界面的多层结构，因此上部BPSG氧化物层的硼（B）不会渗透到半导体衬底中。

公开(公告)号：US20060091777A1

公开(公告)日：2006-05-04

申请号：US11260120

申请日：2005-10-28

申请人： Sung Jung

发明人： Sung Jung

IPC分类号： H01J29/86 ,  H01J29/88 ,  H01J29/92 ,  H01J29/87 ,  H01J5/24

CPC分类号： H01J29/861 ,  H01J2229/862

摘要： A frame for a cathode ray tube including a panel formed with a blend region outside an effective screen of the panel, the blend region having an outer surface curvature having a radius satisfying a condition “20≦Rb≦60 (mm)” where “Rb” represents the outer surface curvature radius, so that it is possible to reduce the weight of the panel without causing a degradation in picture quality, and thus, to reduce manufacturing costs. It is also possible to reduce damage of the panel when the panel is processed in a furnace, and thus, to achieve an enhancement in productivity.

摘要翻译： 一种用于阴极射线管的框架，其包括在面板的有效屏幕外部形成有混合区域的面板，所述混合区域具有满足条件“20 <= Rb <= 60（mm）”的半径的外表面曲率， “Rb”表示外表面曲率半径，从而可以减小面板的重量而不会降低图像质量，从而降低制造成本。 当在炉中处理面板时也可以减小面板的损坏，从而提高生产率。