公开(公告)号：US20110018036A1

公开(公告)日：2011-01-27

申请号：US12636912

申请日：2009-12-14

申请人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

发明人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC分类号： H01L27/085

CPC分类号： G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

摘要翻译： 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

公开(公告)号：US08492831B2

公开(公告)日：2013-07-23

申请号：US12636912

申请日：2009-12-14

申请人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

发明人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC分类号： H01L29/66

CPC分类号： G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

摘要翻译： 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

公开(公告)号：US20110298013A1

公开(公告)日：2011-12-08

申请号：US13081776

申请日：2011-04-07

申请人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

发明人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

IPC分类号： H01L23/52 ,  H01L29/78

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

摘要翻译： 半导体存储器件包括：从衬底的第一区域垂直延伸的半导体区域; 沿垂直方向设置在所述基板的所述第一区域上，但沿着所述半导体区域的侧壁彼此分离的多个栅电极; 设置在所述半导体区域和所述多个栅电极之间的栅介质层; 从衬底的杂质掺杂的第二区域垂直延伸的衬底接触电极; 以及形成为所述基板接触电极和所述多个栅极电极中的至少一个之间的气隙的绝缘区域。

公开(公告)号：US09373400B2

公开(公告)日：2016-06-21

申请号：US14960839

申请日：2015-12-07

申请人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

发明人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/02

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

公开(公告)号：US08492797B2

公开(公告)日：2013-07-23

申请号：US13081776

申请日：2011-04-07

申请人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

发明人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

IPC分类号： H01L23/52 ,  H01L29/78

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

公开(公告)号：US20140293703A1

公开(公告)日：2014-10-02

申请号：US14302025

申请日：2014-06-11

申请人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

发明人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

摘要翻译： 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。

公开(公告)号：US20100195395A1

公开(公告)日：2010-08-05

申请号：US12658072

申请日：2010-02-02

申请人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

发明人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

摘要翻译： 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。

公开(公告)号：US08295089B2

公开(公告)日：2012-10-23

申请号：US12658072

申请日：2010-02-02

申请人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

发明人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

摘要翻译： 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。

公开(公告)号：US20160284729A1

公开(公告)日：2016-09-29

申请号：US15176917

申请日：2016-06-08

申请人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

发明人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC分类号： H01L27/115 ,  H01L23/528 ,  G11C16/10 ,  H01L23/522 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

公开(公告)号：US09478291B2

公开(公告)日：2016-10-25

申请号：US15176917

申请日：2016-06-08

申请人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

发明人： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

摘要翻译： 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。