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1.发明授权Method and device for detecting and controlling an array source signal discharge for a memory erase operation 失效用于检测和控制用于存储器擦除操作的阵列源信号放电的方法和装置
公开(公告)号：US5424992A
公开(公告)日：1995-06-13
申请号：US112484
申请日：1993-08-25
CPC分类号： G11C16/16
摘要： An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging. The pulse converter circuit (12) receives the array source detect signal (ASDET) and generates an erase completion signal (ERCTR) and a pulldown control signal ERCTR.sub.-- to control final discharge of the array source signals (AS) and indicate that normal memory access may resume. The pulse converter circuit (12) also generates a pulldown signal (ERD.sub.--) that controls discharge of the array source signals (AS) by preventing current surges from appearing on the array source signals (AS) during discharge.
摘要翻译： 阵列源信号放电控制器装置（10）包括接收擦除脉冲信号（ERPULSE）的脉冲转换器电路（12）。 脉冲转换器电路（12）将擦除脉冲信号（ERPULSE）转换成脉冲控制信号（ERPCL），随后将其转换为更高的电压电平偏置信号（ECL-）。 较高电压电平偏置信号（ECL-）驱动产生阵列源信号（AS）的阵列源信号发生器电路（16），以擦除由选择电路（17）确定的存储器的特定阵列子部分。 阵列源信号发生器电路（16）还产生阵列源指令信号（ASCOM-），以指示所有阵列源信号（AS）的放电状态。 擦除完成检测电路（18）监视阵列源指令信号（ASCOM-）并产生阵列源检测信号（ASDET），以指示阵列源信号（AS）放电完成。 脉冲转换器电路（12）接收阵列源检测信号（ASDET）并产生擦除完成信号（ERCTR）和下拉控制信号ERCTR-以控制阵列源信号（AS）的最终放电，并指示正常存储器存取 可能会恢复。 脉冲转换器电路（12）还通过在放电期间防止在阵列源信号（AS）上出现电流浪涌来产生控制阵列源信号（AS）的放电的下拉信号（ERD-）。
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公开(公告)号：US5396115A
公开(公告)日：1995-03-07
申请号：US149245
申请日：1993-10-26
CPC分类号： G06F1/28 , G06F1/24 , H03K17/223 , H03K5/04
摘要： The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.
摘要翻译： 本发明的上电复位电路包括电流检测电路，脉冲拉伸电路和电压参考电路。 电压基准电路例如由一个N沟道和一个P沟道MOS晶体管组成。 本发明的电路使用由CMOS晶体管组成的静态参考电压来检测上电状态。 本发明的电路改进了瞬态电源电压Vcc损耗的检测，并检测上升沿和下降沿的电源电压瞬变。
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3.发明授权Circuit and method for detecting column-line shorts in integrated-circuit memories 失效用于检测集成电路存储器中的列线短路的电路和方法
公开(公告)号：US5392248A
公开(公告)日：1995-02-21
申请号：US149242
申请日：1993-10-26
CPC分类号： G11C29/025 , G11C29/02 , G11C29/18 , G11C29/50 , G11C16/04 , G11C2029/5006
摘要： The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.
摘要翻译： 本发明的列线短路检测电路包括一个特殊的测试电路，它关闭字线（15），用于每列列线（18）的N沟道晶体管（23），仅使用最不重要的解码器（19a） 用于输入到测试电路的列地址（20d）和用于检测短路列线（18）之间的电流的传感器（SA）。 因为本发明的列线短路检测电路仅使用最低有效地址作为列解码器（19a）的输入，所以它需要非常少数量的晶体管。
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公开(公告)号：US5657268A
公开(公告)日：1997-08-12
申请号：US560670
申请日：1995-11-20
申请人： Phat C. Truong , Sung-Wei Lin
发明人： Phat C. Truong , Sung-Wei Lin
摘要： In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector. An erasing method includes connecting the wordlines to a reference voltage, connecting at least one deselected common array-source line to each bitline coupled to drains of columns of memory cells in the deselected sector, then biasing at a positive voltage both the deselected common array-source line and said bitlines coupled to drains of memory cells in columns of the deselected sector, and then applying a positive erasing voltage to said common array-source line of the selected sector.
摘要翻译： 在其中每个存储器单元具有耦合到位线的漏极的多扇区非易失性存储器阵列中，每个扇区的每个存储单元具有耦合到公共阵列源极线的源极，第一扇区的一行中的每个存储器单元具有 耦合到字线的控制栅极和另一扇区中的行的每个存储器单元具有耦合到该字线的控制栅极，用于对所述方法的一个扇区中的存储器单元进行编程的方法包括至少连接第二公共数组源极线 耦合到另一扇区中的存储器单元列的排列的每个位线，然后以正电压偏置公共阵列源极线和与另一扇区的列中的存储器单元的漏极耦合的位线，然后施加编程 电压被连接到第一扇区中所选择的单元的控制栅极的选定字线。 擦除方法包括将字线连接到参考电压，将至少一个未选择的公共阵列源线连接到耦合到取消选择的扇区中的存储器单元的列的排列的每个位线，然后以正电压偏置所选择的公共阵列 - 源极线和所述位线耦合到取消选择的扇区的列中的存储器单元的漏极，然后将正的擦除电压施加到所选择的扇区的所述公共阵列源极线。
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公开(公告)号：US5694073A
公开(公告)日：1997-12-02
申请号：US560768
申请日：1995-11-21
申请人： Timothy J. Coots , Phat C. Truong , Sung-Wei Lin , Tim M. Coffman , Ming-Bo Liu , Ronald J. Syzdek
发明人： Timothy J. Coots , Phat C. Truong , Sung-Wei Lin , Tim M. Coffman , Ming-Bo Liu , Ronald J. Syzdek
IPC分类号： G01K7/00 , G01R19/00 , G05F3/24 , G05F3/26 , H03K17/14 , H03K17/16 , H03K17/687 , H03K19/003 , G05F3/02
CPC分类号： G05F3/262 , G05F3/247 , H03K19/00384
摘要： A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).
摘要翻译： 电源电压检测级（11），其提供第一和第二参考电流（IREFP和IREFN），其随着电源电压（Vcc）而变化并分别由第一和第二增益级（12A和12B）耦合到第一和第二增益级 第二温度检测级（13A和13B）。 第一和第二温度检测级（13A和13B）分别增加耦合的参考电流（IREFP和IREFN），以通过使用温度敏感的长沟道晶体管（M34-M37和M42-M45）补偿温度升高， 在输出端子（MIRN和MIRP）提供温度和电源电压补偿输出偏置电压。
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公开(公告)号：US5450417A
公开(公告)日：1995-09-12
申请号：US149243
申请日：1993-10-26
CPC分类号： H03K3/356008 , H03K17/22
摘要： The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.
摘要翻译： 本发明的上电复位测试电路包括两个不平衡锁存器，用于检测瞬态上电复位信号的发生。 瞬态上电复位信号的发生被锁存用于电路测试期间的后续验证。 两个锁存器都设计为在初始上电时默认为低电压输出（Vss）。 其中一个锁存器由上电复位信号设置为高电压输出（Vcc）状态。 另一个锁存器由参考电位输入设置为低电压输出状态。 如果设置的锁存器具有高电压输出，另一个锁存器具有低电压输出，则上电复位电路正常工作。
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公开(公告)号：US5397946A
公开(公告)日：1995-03-14
申请号：US149246
申请日：1993-10-26
CPC分类号： G11C5/143 , G11C16/225
摘要： The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.
摘要翻译： CMOS高电压传感器电路具有包括例如四个N沟道MOS晶体管的电压基准; 一个通道P沟道晶体管; 一个电流镜P沟道MOS晶体管; 以及包括例如两个P沟道MOS晶体管和一个N沟道MOS晶体管的常规高压传感器。 如果输入电压大于参考电压加上两个P沟道阈值电压和电源电压Vcc加上两个P沟道阈值电压，本发明的传感器电路在输出端产生高电压信号。 上电或断电顺序可以是任何顺序，而不会不利地影响本发明的电路的操作。
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公开(公告)号：US5668769A
公开(公告)日：1997-09-16
申请号：US560229
申请日：1995-11-21
IPC分类号： G11C11/41 , G11C7/22 , G11C11/409 , G11C7/00
CPC分类号： G11C7/22
摘要： The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.
摘要翻译： 本发明的方法防止在高频禁用周期的瞬态电流，并且在最小延迟时间之后禁用直流电流路径，从而降低功耗。 本发明包括延迟电路，其功能是防止在低于最小持续时间的间隔下发生芯片禁止时间的DC路径的禁用。 结果是由于瞬态电流，内部电力总线上的不期望的电压降的数量减少。 该方法检测在最小持续时间之前发生的外部芯片禁止脉冲，然后防止这些脉冲掉电内部直流路径。 同时，保持了芯片禁止信号的输出驱动器高阻抗功能。
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公开(公告)号：US5636162A
公开(公告)日：1997-06-03
申请号：US664013
申请日：1996-06-12
申请人： Tim M. Coffman , Sung-Wei Lin , Phat C. Truong
发明人： Tim M. Coffman , Sung-Wei Lin , Phat C. Truong
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.
摘要翻译： 擦除闪存EPROM阵列（AR）的过程包括同时向闪存EPROM阵列（AR）的所有子阵列（S1，S2等）应用一系列擦除脉冲。 在每个擦除脉冲之间，每个子阵列（S1，S2等）的存储单元（10）同时一次检查一行一列，同时检查任何单元（10）是否为 过度消失 如果在程序过程中发现单元（10）被过度擦除的任何时候，都会修正过擦除状态，擦除过程继续进行，但擦除脉冲仅施加于这些子阵列（S1，S2等） ）具有如现有技术的子阵列擦除过程中的未擦除的存储器单元（10）。 在几乎所有情况下，本发明的程序减少了全部擦除时间。
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10.发明授权Segmented, multiple-decoder memory array and method for programming a memory array 失效分段的多解码器存储器阵列和用于编程存储器阵列的方法
公开(公告)号：US5313432A
公开(公告)日：1994-05-17
申请号：US790122
申请日：1991-11-12
申请人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
发明人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
CPC分类号： G11C16/0416 , G11C16/08 , G11C16/12 , G11C5/025 , G11C8/12
摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。
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