公开(公告)号：US20070126005A1

公开(公告)日：2007-06-07

申请号：US11625694

申请日：2007-01-22

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Doug-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Doug-Gyu Kim

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

公开(公告)号：US20050170592A1

公开(公告)日：2005-08-04

申请号：US11080612

申请日：2005-03-16

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L31/0376

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06524876B1

公开(公告)日：2003-02-25

申请号：US09545891

申请日：2000-04-07

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： H01L2100

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06887742B2

公开(公告)日：2005-05-03

申请号：US10302927

申请日：2002-11-25

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/00 ,  H01L21/337

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积并图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06849873B2

公开(公告)日：2005-02-01

申请号：US10303016

申请日：2002-11-25

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Huh ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： In liquid crystal display device having a multi-layer conductive layer, such conductive layer is formed using a photoresist pattern having different thicknesses depending on the position. Upper layer of the gate pad is removed using an etch mask of the photoresist pattern of different thickness. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire. Finally passivation layer is formed and an indium tin oxide layer is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad.

摘要翻译： 在具有多层导电层的液晶显示装置中，使用根据位置具有不同厚度的光致抗蚀剂图案形成这种导电层。 使用不同厚度的光致抗蚀剂图案的蚀刻掩模去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成数据线。 最后，形成钝化层，并且沉积和图案化氧化铟锡层以形成像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06307216B1

公开(公告)日：2001-10-23

申请号：US09533379

申请日：2000-03-22

申请人： Sung-Wook Huh ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Bum-Ki Baek

发明人： Sung-Wook Huh ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Bum-Ki Baek

IPC分类号： H01L2904

CPC分类号： G02F1/1309 ,  G02F2001/136263 ,  G02F2001/136272 ,  H01L27/124

摘要： Disclosed are ring-shaped gate wires and redundancy lines formed on a substrate so that defects due to disconnection of data lines can be readily repaired. The redundancy line is formed in a unit of a pixel, located outside the gate wire and divided into two portions. A gate insulating film is formed thereon, and data lines are formed thereon. Each of the data line overlaps the redundancy line and intersects a portion of the gate wire. A passivation film is formed on the data lines and transparent conductive connect patterns are formed thereon. The transparent connect pattern intersects two adjacent pixels and overlaps the ends of the redundancy lines facing each other. Since the end portions of the redundancy lines are bent out from the direction of the data line, it is not required that the connect pattern overlaps the data line. When the data line is disconnected on the step point where the data line intersects the gate wire, the redundancy lines can be short-circuited to the data line on either side of the disconnection point by using a laser to repair the disconnection.

摘要翻译： 公开了形成在基板上的环形栅极线和冗余线，从而可以容易地修复由于数据线断开引起的缺陷。 冗余线形成为位于栅极线外侧的像素单位，并分成两部分。 在其上形成栅极绝缘膜，并在其上形成数据线。 每条数据线与冗余线重叠，并与栅极线的一部分相交。 在数据线上形成钝化膜，并在其上形成透明导电连接图案。 透明连接图案与两个相邻的像素相交并且与彼此面对的冗余线的端部重叠。 由于冗余线的端部从数据线的方向弯曲，所以不需要连接图案与数据线重叠。 当数据线在数据线与栅极线相交的步进点上断开数据线时，冗余线可以通过使用激光修复断线而与断开点两侧的数据线短路。

公开(公告)号：US07863620B2

公开(公告)日：2011-01-04

申请号：US12574915

申请日：2009-10-07

申请人： Hyang-Shik Kong ,  Sung-Wook Huh ,  Young-Bae Park

发明人： Hyang-Shik Kong ,  Sung-Wook Huh ,  Young-Bae Park

IPC分类号： H01L29/76 ,  H01L21/00

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F2001/136254 ,  H01L21/32134 ,  H01L21/32136 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads. The inspection system for determining whether a thin film transistor substrate is defective, in which the thin film transistor substrate comprises gate wiring including gate lines, gate electrodes and gate pads, and data wiring including source electrodes and drain electrodes, includes a probe pin for contacting the gate pads or data pads and transmitting a corresponding signal, wherein a contact tip at a distal end of the probe pin for contacting the gate pads or the data pads is rounded, and a radius of the rounded contact tip is 2 μm or less, or the rounded contact tip is coated with gold (Au).

摘要翻译： 公开了一种薄膜晶体管基板及其检查系统。 薄膜晶体管基板包括形成在绝缘基板上并包括栅极线的栅极布线，以及连接到栅极线的栅电极和栅极焊盘; 覆盖栅极布线的栅极绝缘层; 形成在所述栅绝缘层上的半导体层; 数据布线形成在栅极绝缘层上并包括数据焊盘; 覆盖数据线的保护层; 辅助焊盘通过形成在保护层中的接触孔连接到数据焊盘; 以及在数据焊盘下方突出预定高度形成的焊盘辅助层。 用于确定薄膜晶体管基板是否缺陷的检查系统，其中薄膜晶体管基板包括包括栅极线，栅电极和栅极焊盘的栅极布线，以及包括源电极和漏电极的数据布线，包括用于接触的探针 所述栅极焊盘或数据焊盘并传输相应的信号，其中用于接触所述栅极焊盘或所述数据焊盘的所述探针的远端处的接触尖端是圆形的，并且所述圆形接触尖端的半径为2μm或更小， 或圆形接触尖端涂有金（Au）。

公开(公告)号：US20050087770A1

公开(公告)日：2005-04-28

申请号：US10986930

申请日：2004-11-15

申请人： Hyang-Shik Kong ,  Sung-Wook Huh ,  Young-Bae Park

发明人： Hyang-Shik Kong ,  Sung-Wook Huh ,  Young-Bae Park

IPC分类号： G02F1/136 ,  H01L21/3213 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L29/73

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F2001/136254 ,  H01L21/32134 ,  H01L21/32136 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads. The inspection system for determining whether a thin film transistor substrate is defective, in which the thin film transistor substrate comprises gate wiring including gate lines, gate electrodes and gate pads, and data wiring including source electrodes and drain electrodes, includes a probe pin for contacting the gate pads or data pads and transmitting a corresponding signal, wherein a contact tip at a distal end of the probe pin for contacting the gate pads or the data pads is rounded, and a radius of the rounded contact tip is 2 μm or less, or the rounded contact tip is coated with gold (Au).

摘要翻译： 公开了一种薄膜晶体管基板及其检查系统。 薄膜晶体管基板包括形成在绝缘基板上并包括栅极线的栅极布线，以及连接到栅极线的栅电极和栅极焊盘; 覆盖栅极布线的栅极绝缘层; 形成在所述栅绝缘层上的半导体层; 数据布线形成在栅极绝缘层上并包括数据焊盘; 覆盖数据线的保护层; 辅助焊盘通过形成在保护层中的接触孔连接到数据焊盘; 以及在数据焊盘下方突出预定高度形成的焊盘辅助层。 用于确定薄膜晶体管基板是否缺陷的检查系统，其中薄膜晶体管基板包括包括栅极线，栅电极和栅极焊盘的栅极布线，以及包括源电极和漏电极的数据布线，包括用于接触的探针 栅极焊盘或数据焊盘并传输相应的信号，其中用于接触栅极焊盘或数据焊盘的探针的远端处的接触尖端是圆形的，并且圆形接触尖端的半径为2μm或更小， 或圆形接触尖端涂有金（Au）。

公开(公告)号：US08294839B2

公开(公告)日：2012-10-23

申请号：US13162515

申请日：2011-06-16

申请人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

发明人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

IPC分类号： G02F1/136

CPC分类号： G02F1/134336 ,  G02F1/1362 ,  G02F1/136286 ,  G02F2001/13606 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/12

摘要： A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on the gate insulating layer. The transparent conductive layer is patterned to form a pixel electrode. An opening is formed at a circumference of the pixel electrode. The opening minimizes misalignment during the manufacturing process and prevents shorts between a data line and the pixel electrode.

摘要翻译： 公开了一种制造薄膜晶体管阵列面板的方法。 在绝缘基板上形成栅极布线图案。 栅极绝缘层形成在栅极布线图案上。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层上形成透明导电层。 图案化透明导电层以形成像素电极。 在像素电极的圆周上形成开口。 该开口使制造过程中的未对准最小化并防止数据线与像素电极之间的短路。

公开(公告)号：US20080073644A1

公开(公告)日：2008-03-27

申请号：US11668345

申请日：2007-01-29

申请人： Hyang-Shik KONG ,  Sung-Wook Huh ,  Young-Bae Park

发明人： Hyang-Shik KONG ,  Sung-Wook Huh ,  Young-Bae Park

IPC分类号： H01L29/04

CPC分类号： G02F1/1362 ,  G02F1/13458 ,  G02F2001/136254 ,  H01L21/32134 ,  H01L21/32136 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads. The inspection system for determining whether a thin film transistor substrate is defective, in which the thin film transistor substrate comprises gate wiring including gate lines, gate electrodes and gate pads, and data wiring including source electrodes and drain electrodes, includes a probe pin for contacting the gate pads or data pads and transmitting a corresponding signal, wherein a contact tip at a distal end of the probe pin for contacting the gate pads or the data pads is rounded, and a radius of the rounded contact tip is 2 μm or less, or the rounded contact tip is coated with gold (Au).

摘要翻译： 公开了一种薄膜晶体管基板及其检查系统。 薄膜晶体管基板包括形成在绝缘基板上并包括栅极线的栅极布线，以及连接到栅极线的栅电极和栅极焊盘; 覆盖栅极布线的栅极绝缘层; 形成在所述栅绝缘层上的半导体层; 数据布线形成在栅极绝缘层上并包括数据焊盘; 覆盖数据线的保护层; 辅助焊盘通过形成在保护层中的接触孔连接到数据焊盘; 以及在数据焊盘下方突出预定高度形成的焊盘辅助层。 用于确定薄膜晶体管基板是否缺陷的检查系统，其中薄膜晶体管基板包括包括栅极线，栅电极和栅极焊盘的栅极布线，以及包括源电极和漏电极的数据布线，包括用于接触的探针 栅极焊盘或数据焊盘并传输相应的信号，其中用于接触栅极焊盘或数据焊盘的探针的远端处的接触尖端是圆形的，并且圆形接触尖端的半径为2μm或更小， 或圆形接触尖端涂有金（Au）。