公开(公告)号：US20120056245A1

公开(公告)日：2012-03-08

申请号：US13155483

申请日：2011-06-08

申请人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy

摘要翻译： 半导体器件包括半导体衬底，栅电极结构，其包括位于半导体衬底的有源区上的栅电极，位于栅电极结构相对侧的有源区中的第一和第二外延区，以及第一和第二硅化物 分别在第一和第二外延区域的上表面上分层。 第一外延区域和第二外延区域包括Si-X，其中X是锗和碳之一，并且第一和第二硅化物层中的每一个的至少一部分不含X并且包括Si-Y，其中Y是金属或 金属合金

公开(公告)号：US08835995B2

公开(公告)日：2014-09-16

申请号：US13155483

申请日：2011-06-08

申请人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

发明人： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC分类号： H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/40 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy.

摘要翻译： 半导体器件包括半导体衬底，栅电极结构，其包括位于半导体衬底的有源区上的栅电极，位于栅电极结构相对侧的有源区中的第一和第二外延区，以及第一和第二硅化物 分别在第一和第二外延区域的上表面上分层。 第一外延区域和第二外延区域包括Si-X，其中X是锗和碳之一，并且第一和第二硅化物层中的每一个的至少一部分不含X并且包括Si-Y，其中Y是金属或 金属合金。

公开(公告)号：US20110104869A1

公开(公告)日：2011-05-05

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/762

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US08883651B2

公开(公告)日：2014-11-11

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L21/324

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。

公开(公告)号：US09466721B1

公开(公告)日：2016-10-11

申请号：US14978155

申请日：2015-12-22

申请人： Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

发明人： Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/7848

摘要： A semiconductor device may include a fin active region including a lower fin active region surrounded by a device isolation layer and an upper fin active region protruding from a top surface of the device isolation layer, a gate pattern disposed on top and side surfaces of the upper fin active region, and a source/drain region formed in the fin active region located at a side of the gate pattern. The gate pattern extends onto the device isolation region. The source/drain region includes a trench and epitaxial layers that fill the trench. Sidewalls of the trench include first sidewalls and second sidewalls that connect the first sidewalls to a bottom surface of the trench. The bottom surface of the trench is located at a lower level than the top surface of the device isolation layer beneath the gate pattern, and the second sidewalls of the trench have inclined {111} planes.

摘要翻译： 半导体器件可以包括鳍状物活性区域，其包括被器件隔离层包围的下部翅片有源区域和从器件隔离层的顶表面突出的上部翅片有源区域，设置在上部的顶部和侧面上的栅极图案 鳍状物活性区域和形成在位于栅极图案侧的鳍状物活性区域中的源极/漏极区域。 栅极图案延伸到器件隔离区域上。 源/漏区包括填充沟槽的沟槽和外延层。 沟槽的侧壁包括将第一侧壁连接到沟槽的底表面的第一侧壁和第二侧壁。 沟槽的底表面位于比栅极图案下方的器件隔离层的顶表面更低的水平处，并且沟槽的第二侧壁具有倾斜的{111}平面。

公开(公告)号：US08497533B2

公开(公告)日：2013-07-30

申请号：US13554038

申请日：2012-07-20

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US08268687B2

公开(公告)日：2012-09-18

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US20160284837A1

公开(公告)日：2016-09-29

申请号：US14978155

申请日：2015-12-22

申请人： Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

发明人： Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/7848

摘要： A semiconductor device may include a fin active region including a lower fin region surrounded by a device isolation layer and an upper fin active region protruding from a top surface of the device isolation layer, a gate pattern disposed on top and side surfaces of the upper fin active region, and a source/drain region formed in the fin active region located at a side of the gate pattern. The gate pattern extends onto the device isolation region. The source/drain region includes a trench and epitaxial layers that fill the trench. Sidewalls of the trench include first sidewalls and second sidewalls that connect the first sidewalls to a bottom surface of the trench. The bottom surface of the trench is located at a lower level than the top surface of the device isolation layer beneath the gate pattern, and the second sidewalk of the trench have inclined {111} planes.

摘要翻译： 半导体器件可以包括翅片有源区，包括由器件隔离层围绕的下鳍区域和从器件隔离层的顶表面突出的上翅片有源区，设置在上翅片的顶表面和侧表面上的栅极图案 有源区，以及形成在位于栅极图案侧的鳍状物活性区域中的源极/漏极区域。 栅极图案延伸到器件隔离区域上。 源极/漏极区域包括填充沟槽的沟槽和外延层。 沟槽的侧壁包括将第一侧壁连接到沟槽的底表面的第一侧壁和第二侧壁。 沟槽的底表面位于比栅极图案下方的器件隔离层的顶表面更低的水平处，并且沟槽的第二人行道具有倾斜的{111}平面。

公开(公告)号：US20130045589A1

公开(公告)日：2013-02-21

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/20 ,  H01L21/425

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。