公开(公告)号：US07361990B2

公开(公告)日：2008-04-22

申请号：US11082298

申请日：2005-03-17

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/48 ,  H01L21/00 ,  H05K7/10

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US20080142994A1

公开(公告)日：2008-06-19

申请号：US12036928

申请日：2008-02-25

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/52

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US20070257365A1

公开(公告)日：2007-11-08

申请号：US11777878

申请日：2007-07-13

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

摘要翻译： 一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。 所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。 所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。 封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

公开(公告)号：US07265034B2

公开(公告)日：2007-09-04

申请号：US11174710

申请日：2005-07-05

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L21/46

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

摘要翻译： 提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。 使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。 在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。 两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。 这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。

公开(公告)号：US07642631B2

公开(公告)日：2010-01-05

申请号：US11777878

申请日：2007-07-13

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L23/02

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

摘要翻译： 一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。 所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。 所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。 封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

公开(公告)号：US07491624B2

公开(公告)日：2009-02-17

申请号：US11610752

申请日：2006-12-14

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US07170159B1

公开(公告)日：2007-01-30

申请号：US11160753

申请日：2005-07-07

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US20070087479A1

公开(公告)日：2007-04-19

申请号：US11610752

申请日：2006-12-14

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US20070007649A1

公开(公告)日：2007-01-11

申请号：US11160753

申请日：2005-07-07

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US07662665B2

公开(公告)日：2010-02-16

申请号：US11655844

申请日：2007-01-22

申请人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

发明人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

摘要翻译： 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并且与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。