公开(公告)号：US20080142994A1

公开(公告)日：2008-06-19

申请号：US12036928

申请日：2008-02-25

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/52

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US07361990B2

公开(公告)日：2008-04-22

申请号：US11082298

申请日：2005-03-17

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Chung Yu Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/48 ,  H01L21/00 ,  H05K7/10

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US20070257365A1

公开(公告)日：2007-11-08

申请号：US11777878

申请日：2007-07-13

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

摘要翻译： 一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。 所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。 所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。 封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

公开(公告)号：US07265034B2

公开(公告)日：2007-09-04

申请号：US11174710

申请日：2005-07-05

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L21/46

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

摘要翻译： 提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。 使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。 在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。 两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。 这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。

公开(公告)号：US07642631B2

公开(公告)日：2010-01-05

申请号：US11777878

申请日：2007-07-13

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L23/02

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

摘要翻译： 一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。 所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。 所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。 封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

公开(公告)号：US07851331B2

公开(公告)日：2010-12-14

申请号：US11563490

申请日：2006-11-27

申请人： Szu Wei Lu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Hua-Shu Wu ,  Jerry Tzou

发明人： Szu Wei Lu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Hua-Shu Wu ,  Jerry Tzou

IPC分类号： H01L21/46

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/495 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.

摘要翻译： 半导体结构包括第一基板和粘合在第一基板上的第二基板。 第一衬底包括形成在第一衬底上的钝化层。 钝化层包括至少一个第一开口，暴露在第一衬底上形成的第一焊盘。 第二基板包括与第一开口对准并面向第一开口的至少一个第二开口。

公开(公告)号：US07656042B2

公开(公告)日：2010-02-02

申请号：US11393050

申请日：2006-03-29

申请人： Mirng-Ji Lii ,  Szu Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。

公开(公告)号：US20080122114A1

公开(公告)日：2008-05-29

申请号：US11563490

申请日：2006-11-27

申请人： Szu Wei Lu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Hua-Shu Wu ,  Jerry Tzou

发明人： Szu Wei Lu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Hua-Shu Wu ,  Jerry Tzou

IPC分类号： H01L21/50 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/495 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.

摘要翻译： 半导体结构包括第一基板和粘合在第一基板上的第二基板。 第一衬底包括形成在第一衬底上的钝化层。 钝化层包括至少一个第一开口，暴露在第一衬底上形成的第一焊盘。 第二基板包括与第一开口对准并面向第一开口的至少一个第二开口。

公开(公告)号：US07851916B2

公开(公告)日：2010-12-14

申请号：US11082675

申请日：2005-03-17

申请人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Wei Lu

发明人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Wei Lu

IPC分类号： H01L21/20

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/81 ,  H01L29/045 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

摘要翻译： 公开了一种用于更好地封装半导体器件的方法和系统。 在一个示例中，半导体器件封装包括封装衬底，至少一个具有取向<100>的裸片放置在衬底上，其中在封装衬底和裸片之间形成电连接，以及将裸片附接到衬底 其中底部填充圆角在其至少一侧上达到小于模具厚度的60％。

公开(公告)号：US08580683B2

公开(公告)日：2013-11-12

申请号：US13246556

申请日：2011-09-27

申请人： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

发明人： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC分类号： H01L23/28

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

摘要翻译： 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。