公开(公告)号：US20230020933A1

公开(公告)日：2023-01-19

申请号：US17377796

申请日：2021-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wen-Yuan CHEN ,  Chun-Chung SU ,  Jon-Hsu HO ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L27/088 ,  H01L21/764

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US20240313052A1

公开(公告)日：2024-09-19

申请号：US18674989

申请日：2024-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Jiun KUANG ,  Meng-Yu LIN ,  Chung-Wei WU ,  Chun-Fu CHENG

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.

公开(公告)号：US20230262986A1

公开(公告)日：2023-08-17

申请号：US17669802

申请日：2022-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wen-Ling LU ,  Chia-En HUANG ,  Ya-Yun CHENG ,  Yi-Ching LIU ,  Huan-Sheng WEI ,  Chung-Wei WU

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  G11C5/06

CPC分类号： H01L27/11597 ,  G11C5/063 ,  H01L27/11587

摘要： A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.

公开(公告)号：US20230246026A1

公开(公告)日：2023-08-03

申请号：US18132924

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Chun-Chung SU ,  Chung-Wei WU ,  Jon-Hsu HO ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH ,  Wen-Yuan CHEN ,  Zhi-Qiang WU

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/06

CPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US20240339355A1

公开(公告)日：2024-10-10

申请号：US18743574

申请日：2024-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Yu LIN ,  Zhiqiang WU ,  Chung-Wei WU ,  Chun-Fu CHENG

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76802 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897

摘要： The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20230335617A1

公开(公告)日：2023-10-19

申请号：US17724434

申请日：2022-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mahaveer Sathaiya DHANYAKUMAR ,  Cheng-Ting CHUNG ,  Chien-Hong CHEN ,  Jin CAI ,  Chung-Wei WU

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

摘要： A method includes forming a dielectric layer over a substrate; forming a carbon nanotube (CNT) over the dielectric layer; forming a dummy gate structure over the CNT; forming gate spacers on opposite sidewalls of the dummy gate structure; forming source/drain epitaxy structures on opposite sides of the dummy gate structure and in contact with opposite sidewalls of the CNT; replacing the dummy gate structure with a metal gate structure; and forming source/drain contacts over the source/drain epitaxy structures, respectively.

公开(公告)号：US20230178603A1

公开(公告)日：2023-06-08

申请号：US18102812

申请日：2023-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Jiun Kuang ,  Meng-Yu Lin ,  Chun-Fu Cheng ,  Chung-Wei WU

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L29/6656 ,  H01L29/66553 ,  H01L21/823431 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0653

摘要： Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.

公开(公告)号：US20230042480A1

公开(公告)日：2023-02-09

申请号：US17966086

申请日：2022-10-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/45

摘要： Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; and a fourth epitaxial layer formed on the third epitaxial layer of the second source/drain feature.

公开(公告)号：US20220278196A1

公开(公告)日：2022-09-01

申请号：US17187320

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Jiun Kuang ,  Meng-Yu Lin ,  Chun-Fu Cheng ,  Chung-Wei WU

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.

公开(公告)号：US20240186388A1

公开(公告)日：2024-06-06

申请号：US18434875

申请日：2024-02-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L29/417 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45

CPC分类号： H01L29/41791 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/45

摘要： Semiconductor device includes a substrate having a plurality of fins formed from the substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin of the plurality of fins, and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer comprising a first facet and a second facet connecting to the first facet, a second source/drain feature disposed adjacent to the first source/drain feature, the second source/drain feature comprising a first epitaxial layer in contact with a second fin of the plurality of fins a second epitaxial layer formed over the first epitaxial layer of the second source/drain feature, the second epitaxial layer of the second source/drain feature comprising a third facet and a fourth facet connecting to the third facet, and a third epitaxial layer comprising a first center portion disposed above and in contact with the first facet and the second facet, and a second center portion disposed above and in contact with the third facet and the fourth facet.