公开(公告)号：US20240088246A1

公开(公告)日：2024-03-14

申请号：US18510991

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/26513 ,  H01L21/32139 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/401 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US11812608B2

公开(公告)日：2023-11-07

申请号：US17316278

申请日：2021-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsun-Kai Tsao ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shun-Shing Yang ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  ShihKuang Yang

IPC: H10B41/41 ,  H01L21/28 ,  H01L29/423 ,  H10B41/30 ,  H01L21/3105

CPC classification number: H10B41/41 ,  H01L21/31056 ,  H01L29/40114 ,  H01L29/42328 ,  H10B41/30

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US20230290748A1

公开(公告)日：2023-09-14

申请号：US17841112

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Pai Chi Chou ,  Ya-Chi Hung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.

公开(公告)号：US20230290411A1

公开(公告)日：2023-09-14

申请号：US18321975

申请日：2023-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  G11C11/16 ,  H10B12/00 ,  H10B41/30

CPC classification number: G11C16/08 ,  G11C11/1657 ,  H10B12/053 ,  H10B41/30

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US20230170328A1

公开(公告)日：2023-06-01

申请号：US17702068

申请日：2022-03-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Wen-Tuo Huang ,  Chia-Sheng Lin ,  Wei Chuang Wu ,  Shih Kuang Yang ,  Chung-Jen Huang ,  Shun-Kuan Lin ,  Chien Lin Liu ,  Ping-Tzu Chen ,  Yung Chun Tu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2225/06541 ,  H01L2224/80001

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

公开(公告)号：US20210399103A1

公开(公告)日：2021-12-23

申请号：US17462444

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/40 ,  H01L21/265 ,  H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/28

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US11785770B2

公开(公告)日：2023-10-10

申请号：US18079047

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L21/768 ,  H10B41/30 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US08890232B2

公开(公告)日：2014-11-18

申请号：US14176968

申请日：2014-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Hsiang Yang ,  Chieh-Fei Chiu ,  Yu-Ling Hsu

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11517 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

公开(公告)号：US12136627B2

公开(公告)日：2024-11-05

申请号：US17572891

申请日：2022-01-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Tuo Huang ,  Hsin Fu Lin ,  Wei Cheng Wu

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/12

Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

公开(公告)号：US20240088139A1

公开(公告)日：2024-03-14

申请号：US18516311

申请日：2023-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY , LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.